Methods and apparatus for testing a clock signal

Abstract

Techniques test a clock signal by comparing different portions of that clock signal to each other. Such techniques enable the detection of a clock signal having anomalies such as missing pulses or occasional delayed pulses. In one arrangement, a data communications device has a clock signal generator, processing circuitry and a test circuit, both of which are coupled to the clock signal generator. The clock signal generator provides a clock signal. The processing circuitry uses the clock signal to receive data elements on a set of input ports, and to transmit the data elements on a set of output ports. The test circuit includes a node that receives the clock signal, a comparison circuit that provides a comparison signal based on a comparison between the clock signal and a delayed copy of the clock signal, and an output circuit that provides a result signal based on the comparison signal.

1. A method for testing a clock signal, comprising the steps of:
 receiving a clock signal, the clock signal originating from a first clock signal generator;  
 generating a comparison between the clock signal and a delayed copy of the clock signal, the step of generating the comparison including the step of comparing an initial portion of the clock signal to a subsequent portion of the clock signal to identify irregularities in the clock signal;  
 providing a result signal based on the comparison between the clock signal and the delayed copy of the clock signal; and  
 maintaining selection of the first clock signal generator when the result signal has a first value, and switching selection from the first clock signal generator to a second clock signal generator when the result signal has a second value.  
 
   
   
     2. The method of  claim 1  wherein the step of comparing includes the steps of:
 delaying a copy of the clock signal for a predetermined time interval to form the delayed copy of the clock signal; and  
 comparing the clock signal with the delayed copy of the clock signal to compare the initial portion with the subsequent portion.  
 
   
   
     3. The method of  claim 2  wherein the step of delaying includes the step of passing the copy of the clock signal through a set of delay buffers. 
   
   
     4. The method of  claim 2  wherein the step of delaying includes the step of passing the copy of the clock signal through an elongated trace of conductive material. 
   
   
     5. The method of  claim 1  wherein the step of providing the result signal includes the step of:
 providing a comparison signal, which indicates the comparison between the clock signal and the delayed copy of the clock signal, to a trigger circuit having an output that outputs the result signal, the result signal having a constant level when the clock signal and the delayed copy of the clock signal match and a square pulse when the clock signal and the delayed copy of the clock signal do not match.  
 
   
   
     6. The method of  claim 1  wherein the step of providing includes the step of:
 outputting, as the result signal, (i) a first signal value when the initial portion of the clock signal substantially matches the subsequent portion of the clock signal, and (ii) a second signal value when the initial portion of the clock signal substantially does not match the subsequent portion of the clock signal.  
 
   
   
     7. The method of  claim 1  wherein the step of receiving includes the step of:
 obtaining the clock signal from a terminal connected to an input of an operating circuit that operates in a normal operating mode during the steps of generating the comparison and providing the result signal.  
 
   
   
     8. The method of  claim 7  wherein the operating circuit includes data communications circuitry that receives data elements through a set of input ports and transmits the data elements through a set of output ports in response to the clock signal, and wherein the steps of receiving, generating and providing occur concurrently in an ongoing manner and while the data communications circuitry receives data elements through the set of input ports and transmits the data elements through the set of output ports in response to the clock signal. 
   
   
     9. The method of  claim 1  wherein maintaining and switching include the step of:
 directing an output circuit to provide (i) the clock signal from the first clock signal generator when the result signal has a first value indicating correctness of the clock signal from the first clock signal generator, and (ii) a backup signal when the result signal has a second value indicating incorrectness of the clock signal from the first clock signal generator.  
 
   
   
     10. A method for testing a clock signal, comprising the steps of:
 receiving a clock signal;  
 generating a comparison between the clock signal and a delayed copy of the clock signal; and providing a result signal based on the comparison between the clock signal and the delayed copy of the clock signal, wherein the step of generating the comparison includes the step of:  
 providing the clock signal to a first input of an XOR circuit; and  
 providing the delayed copy of the clock signal to a second input of the XOR circuit, the output of the XOR circuit providing an output signal having an asserted level when the clock signal and the delayed copy of the clock signal do not instantaneously match, and a de-asserted level when the clock signal and the delayed copy of the clock signal instantaneously match.  
 
   
   
     11. A method for testing a clock signal, comprising the steps of:
 receiving a clock signal;  
 generating a comparison between the clock signal and a delayed copy of the clock signal; and providing a result signal based on the comparison between the clock signal and the delayed copy of the clock signal, wherein the step of providing the result signal includes the step of:  
 providing a comparison signal, which indicates the comparison between the clock signal and the delayed copy of the clock signal, to an RC circuit having an output that provides a tuned signal based on the comparison signal.  
 
   
   
     12. A test circuit for testing a clock signal, comprising:
 a node that receives a clock signal, the clock signal originating from a first clock signal generator;  
 a comparison circuit, coupled to the node, that provides a comparison signal based on a comparison between the clock signal and a delayed copy of the clock signal; the comparison circuit, when providing the comparison signal being configured to compare an initial portion of the clock signal to a subsequent portion of the clock signal to identify irregularities in the clock signal; and  
 an output circuit, coupled to the comparison circuit, that provides a result signal based on the comparison signal; the reset signal provided by the output circuit being configured to maintain selection of the first clock signal generator when the result signal has a first value, and switch selection from the first clock signal generator to a second clock signal generator when the result signal has a second value.  
 
   
   
     13. The test circuit of  claim 12  wherein the comparison circuit includes:
 a delay circuit that delays a copy of the clock signal for a predetermined time interval to form the delayed copy of the clock signal; and  
 compare circuitry, coupled to the delay circuit, that compares the clock signal with the delayed copy of the clock signal to compare the initial portion with the subsequent portion.  
 
   
   
     14. The test circuit of  claim 13  wherein the delay circuit includes a set of delay buffers connected in a cascading manner. 
   
   
     15. The test circuit of  claim 13  wherein the delay circuit includes an elongated trace of conductive material. 
   
   
     16. The test circuit of  claim 13  wherein the output circuit, when providing the result signal, is configured to:
 output, as the result signal, (i) a first signal value when the initial portion of the clock signal substantially matches the subsequent portion of the clock signal, and (ii) a second signal value when the initial portion of the clock signal substantially does not match the subsequent portion of the clock signal.  
 
   
   
     17. The test circuit of  claim 12  wherein the output circuit includes:
 a trigger circuit having an input coupled to the comparison circuit, and an output that outputs the result signal, the result signal having a constant level when the clock signal and the delayed copy of the clock signal match and a square pulse when the clock signal and the delayed copy of the clock signal do not match.  
 
   
   
     18. A test circuit for testing a clock signal, comprising:
 a node that receives a clock signal;  
 a comparison circuit, coupled to the node, that provides a comparison signal based on a comparison between the clock signal and a delayed copy of the clock signal; and  
 an output circuit, coupled to the comparison circuit, that provides a result signal based on the comparison signal, wherein the comparison circuit includes:  
 an XOR circuit having a first input that receives the clock signal, a second input that receives the delayed copy of the clock signal, and an output that provides an output signal having an asserted level when the clock signal and the delayed copy of the clock signal do not instantaneously match, and a de-asserted level when the clock signal and the delayed copy of the clock signal instantaneously match.  
 
   
   
     19. A test circuit for testing a clock signal, comprising:
 a node that receives a clock signal;  
 a comparison circuit, coupled to the node, that provides a comparison signal based on a comparison between the clock signal and a delayed copy of the clock signal; and  
 an output circuit, coupled to the comparison circuit, that provides a result signal based on the comparison signal, wherein the output circuit includes:  
 an RC circuit having an input coupled to the comparison circuit, and an output that provides a tuned signal based on the comparison signal.  
 
   
   
     20. A data communications device, comprising:
 a first clock signal generator that provides a clock signal;  
 processing circuitry, coupled to the first clock signal generator, that uses the clock signal to receive data elements on a set of input ports, and to transmit the data elements on a set of output ports; and  
 a test circuit, coupled to the first clock signal generator, that tests the clock signal provided by the first clock signal generator, the test circuit including (i) a node that receives the clock signal, (ii) a comparison circuit, coupled to the node, that provides a comparison signal based on a comparison between the clock signal and a delayed copy of the clock signal, and (iii) an output circuit, coupled to the comparison circuit, that provides a result signal based on the comparison signal,  
 wherein the comparison circuit, when providing the comparison signal, is configured to compare an initial portion of the clock signal to a subsequent portion of the clock signal to identify irregularities in the clock signal, and  
 wherein the reset signal provided by the output circuit is configured to maintain selection of the first clock signal generator when the result signal has a first value, and switch selection from the first clock signal generator to a second clock signal generator when the result signal has a second value.  
 
   
   
     21. The data communications device of  claim 20  wherein the comparison circuit includes:
 a delay circuit that delays a copy of the clock signal for a predetermined time interval to form the delayed copy of the clock signal; and  
 compare circuitry, coupled to the delay circuit, that compares the clock signal with the delayed copy of the clock signal to compare the initial portion with the subsequent portion.  
 
   
   
     22. The data communications device of  claim 21  wherein the delay circuit includes a set of delay buffers connected in a cascading manner. 
   
   
     23. The data communications device of  claim 21  wherein the delay circuit includes an elongated trace of conductive material. 
   
   
     24. The data communications device of  claim 20  wherein the output circuit of the test circuit, when providing the result signal, is configured to:
 output, as the result signal, (i) a first signal value when the initial portion of the clock signal substantially matches the subsequent portion of the clock signal, and (ii) a second signal value when the initial portion of the clock signal substantially does not match the subsequent portion of the clock signal.  
 
   
   
     25. A data communications device, comprising:
 a clock signal generator that provides a clock signal;  
 processing circuitry, coupled to the clock signal generator, that uses the clock signal to receive data elements on a set of input ports, and to transmit the data elements on a set of output ports; and  
 a test circuit, coupled to the clock signal generator, that tests the clock signal provided by the clock signal generator, the test circuit including (i) a node that receives the clock signal, (ii) a comparison circuit, coupled to the node, that provides a comparison signal based on a comparison between the clock signal and a delayed copy of the clock signal, and (iii) an output circuit, coupled to the comparison circuit, that provides a result signal based on the comparison signal, wherein the comparison circuit includes:  
 an XOR circuit having a first input that receives the clock signal, a second input that receives the copy of the clock signal, and an output that provides an output signal having an asserted level when the clock signal and the delayed copy of the clock signal do not instantaneously match, and a de-asserted level when the clock signal and the delayed copy of the clock signal instantaneously match.  
 
   
   
     26. A data communications device, comprising:
 a clock signal generator that provides a clock signal;  
 processing circuitry, coupled to the clock signal generator, that uses the clock signal to receive data elements on a set of input ports, and to transmit the data elements on a set of output ports; and  
 a test circuit, coupled to the clock signal generator, that tests the clock signal provided by the clock signal generator, the test circuit including (i) a node that receives the clock signal, (ii) a comparison circuit, coupled to the node, that provides a comparison signal based on a comparison between the clock signal and a delayed copy of the clock signal, and (iii) an output circuit, coupled to the comparison circuit, that provides a result signal based on the comparison signal, wherein the output circuit includes:  
 an RC circuit having an input coupled to the comparison circuit, and an output that provides a tuned signal based on the comparison signal.