Ultra low power analog to digital converter

Abstract

An analog-to-digital converter for ultra low power applications, such as pacemakers, has a digitizer for producing a digital output signal from a sampled analog input signal. The digitizer is normally in off state to save current. A sample-and-hold circuit stores a plurality of successive samples of the analog input signal. A control element turns on the digitizer in response to an activation signal, sequentially applies the stored samples to the digitizer in response to the activation signal and thus reconstructs the signal as it existed prior to the activation signal.

1. An analog-to-digital converter, comprising:
 an input for receiving an analog input signal;  
 a digitizer for producing a digital output signal, said digitizer being switchable, in response to an activation signal, between a power saving mode, in which said digitizer is inactive, and a reconstruction mode, in which said digitizer is operational;  
 a circuit element for generating said activation signal in response to a trigger event; a sample-and-hold circuit having a plurality of storage elements, said sample-and-hold circuit storing successive groups of samples of said analog input signal; a first set of switch elements connecting said input to said respective storage elements of said sample-and-hold circuit;  
 a second set of switch elements connecting said respective storage elements of said sample-and-hold circuit to said digitizer; and  
 a control element for controlling said first set of switch elements to continually apply incoming samples of said analog input signal in a cyclic fashion to said storage elements, said control element further controlling said second set of switch elements when said digitizer is in said reconstruction mode to sequentially apply said samples of said analog input signal stored in said storage elements to said digitizer with a predetermined delay relative to said incoming samples so as to permit said digitizer to output a portion of said input signal that arrived at said input prior to the occurrence of said activation signal.  
 
   
   
     2. An analog-to-digital converter as claimed in  claim 1 , wherein said storage elements each comprise a capacitor. 
   
   
     3. An analog-to-digital converter as claimed in  claim 2 , comprising eight said capacitors. 
   
   
     4. An analog-to-digital converter as claimed in  claim 1 , further comprising a comparator for generating said activation signal in response to said input signal reaching a threshold level. 
   
   
     5. An analog-to-digital converter as claimed in  claim 1 , wherein said control element is a state machine. 
   
   
     6. A method of converting an analog signal to a digital signal, comprising:
 feeding successive samples of said analog signal to a sample-and-hold circuit;  
 storing groups of successive samples of said input signal in said sample-and-hold circuit;  
 providing a digitizer for producing a digital output signal, said digitizer being switchable, in response to an activation signal, between a power saving mode, in which said digitizer is inactive, and a reconstruction mode, in which said digitizer is operational;  
 generating said activation signal to switch said digitizer into said reconstruction mode in response to a trigger event; and  
 after generating said activation signal, sequentially applying said stored samples with a delay of at least one sample period relative to incoming samples to said digitizer so as to permit said digitizer to output a portion of said input signal that arrived at said input prior to the occurrence of said activation signal.  
 
   
   
     7. A method as claimed in  claim 6 , wherein said samples are stored in a series of sampling circuits, each connected to said digitizer through respective output switches, and said samples are sequentially applied to said digitizer with a delay by controlling said output switches. 
   
   
     8. A method as claimed in  claim 7 , wherein said activation signal is generated by comparing said input signal with a predetermined threshold. 
   
   
     9. A method as claimed in  claim 8 , wherein said sampling circuits each comprise a capacitor. 
   
   
     10. A method as claimed in  claim 9 , wherein said sampling circuits comprise eight said capacitors. 
   
   
     11. A pacemaker comprising:
 a front end for receiving an analog input signal including a comparator for comparing said input signal with a threshold value, said front end generating an activation signal when said input signal reaches said threshold value;  
 a sample-and-hold circuit including storage elements for storing successive groups of samples of said input signal;  
 a digitizer for producing a digital output signal, said digitizer being switchable, in response to said activation signal, between a power saving mode, in which said digitizer is inactive, and a reconstruction mode, in which said digitizer is operational; and  
 a control element for sequentially applying incoming samples of said analog input signal in a cyclic fashion to said storage elements, said control element further, when said digitizer is in said reconstruction mode, sequentially applying samples of said analog input signal stored in said storage elements to said digitizer with a predetermined delay relative to said incoming samples so as to permit said digitizer to output a portion of said input signal that arrived at said input prior to the occurrence of said activation signal.  
 
   
   
     12. A pacemaker as claimed in  claim 11 , wherein said storage elements are connected to said digitizer through respective output switches controlled by said control element. 
   
   
     13. A pacemaker as claimed in  claim 12 , wherein said storage elements are each connected to an input through respective input switches controlled by said control element. 
   
   
     14. A pacemaker as claimed in  claim 11 , further comprising a RAM for storing said digitized version of said input signal as it existed prior to said activation signal. 
   
   
     15. A pacemaker as claimed in  claim 11 , wherein said control element is a state machine.