Phase detection circuit and receiver

Abstract

A quadrant deciding section decides the quadrant to which a received signal belongs based on a baseband signal. A rotation projector rotates the received signal and projects the rotated signal to a straight line that intersects orthogonally at the origin with a straight line that bisects the decided quadrant. An integrator integrates the signal after the projection. A one-bit quantizer quantizes the integration result by deciding the sign of the integration result. A delay circuit delays the quantized signal by a predetermined time. An adder adds the decision result and the quantized signal modulo the phase 2π. A low-pass filter sequentially latches phase values after the addition with internal shift registers, converts the phase value to a prescribed specific value when the phase values that cross over 2π exist in the whole data within the registers, and averages the phase values.

1. A phase detecting circuit comprising:
 a first quantizing unit that quantizes a phase of a received baseband signal;  
 a converting and selecting unit that linearly converts the received signal based on a predetermined rule, and selectively outputs the signal after the linear conversion;  
 an integrating unit that integrates the output from the converting and selecting unit;  
 a second quantizing unit that quantizes the integration result by deciding the sign of the integration result;  
 a delay unit that delays the output from the second quantizing unit by a predetermined first time, and outputs the delayed signal to the converting and selecting unit;  
 an adding unit that adds the output from the first quantizing unit and the output from the second quantizing unit modulo the quantized value of the phase 2π; and  
 a low-pass filter unit that sequentially latches phase values after the addition with internal shift registers, converts the whole data within the shift registers based on a predetermined rule when the phase values that cross over the quantized value of the phase 2π it exist in the whole data, does not carry out the conversion when the phase values that cross over the quantized value of the phase 2π do not exist, averages the phase values in this state, and outputs the phase value after smoothing quantization noise.  
 
   
   
     2. The phase detecting circuit according to  claim 1 , wherein the first quantizing unit, the converting and selecting unit, the integrating unit, the second quantizing unit, the delay unit, and the adding unit constitute a delta sigma modulator. 
   
   
     3. The phase detecting circuit according to  claim 2 , further comprising a sample holding circuit unit that holds the received baseband signal at a constant level during a predetermined second time, at a pre-stage of the delta sigma modulator. 
   
   
     4. The phase detecting circuit according to  claim 2 , wherein the delta sigma modulator comprises a plurality of stages of integrators. 
   
   
     5. The phase detecting circuit according to  claim 4 , further comprising a sample holding circuit unit that holds the received baseband signal at a constant level during a predetermined second time, at a pre-stage of the delta sigma modulator. 
   
   
     6. A phase detecting circuit comprising:
 a first quantizing unit that quantizes the phase of a received baseband signal;  
 a converting and selecting unit that linearly converts the received signal based on a predetermined rule, and selectively outputs the signal after the linear conversion;  
 an integrating unit that integrates the output from the converting and selecting unit;  
 a second quantizing unit that quantizes the integration result by deciding the sign of the integration result based on the output from the first quantizing unit;  
 a delay unit that delays the output from the second quantizing unit by a predetermined time, and outputs the delayed signal to the converting and selecting unit;  
 an adding unit that adds the output from the first quantizing unit and the output from the second quantizing unit modulo the quantized value of the phase 2π; and  
 a low-pass filter unit that sequentially latches phase values after the addition with internal shift registers, converts the whole data within the shift registers based on a predetermined rule when the phase values that cross over the quantized value of the phase 2π exist in the whole data, does not carry out the conversion when the phase values that cross over the quantized value of the phase 2π do not exist, averages the phase values in this state, and outputs the phase value after smoothing quantization noise.  
 
   
   
     7. The phase detecting circuit according to  claim 6 , wherein the first quantizing unit, the converting and selecting unit, the integrating unit, the second quantizing unit, the delay unit, and the adding unit constitute a delta sigma modulator. 
   
   
     8. The phase detecting circuit according to  claim 7 , further comprising a sample holding circuit unit that holds the received baseband signal at a constant level during a predetermined second time, at a pre-stage of the delta sigma modulator. 
   
   
     9. The phase detecting circuit according to  claim 7 , wherein the delta sigma modulator comprises stages of integrators. 
   
   
     10. The phase detecting circuit according to  claim 9 , further comprising a sample holding circuit unit that holds the received baseband signal at a constant level during a predetermined second time, at a pre-stage of the delta sigma modulator. 
   
   
     11. A receiver comprising:
 a first quantizing unit that quantizes the phase of a received baseband signal;  
 a converting and selecting unit that linearly converts the received baseband signal based on a predetermined rule, and selectively outputs the signal after the linear conversion;  
 an integrating unit that integrates the output from the converting and selecting unit;  
 a second quantizing unit that quantizes the integration result by deciding the sign of the integration result;  
 a delay unit that delays the output from the second quantizing unit by a predetermined first time, and outputs the delayed signal to the converting and selecting unit;  
 an adding unit that adds the output from the first quantizing unit and the output from the second quantizing unit modulo the quantized value of the phase 2π;  
 a low-pass filter unit that sequentially latches phase values after the addition with internal shift registers, converts the whole data within the shift registers based on a predetermined rule when the phase values that cross over the quantized value of the phase 2π exist in the whole data, does not carry out the conversion when the phase values that cross over the quantized value of the phase 2π do not exist, averages the phase values in this state, and outputs the phase value after smoothing quantization noise; and  
 a demodulator that demodulates the reception data based on the phase value,  
 wherein the first quantizing unit, the converting and selecting unit, the integrating unit, the second quantizing unit, the delay unit, and the adding unit constitute a delta sigma modulator.  
 
   
   
     12. The receiver according  claim 11 , wherein differential inputs are applied to the first quantizing unit and the converting and selecting unit. 
   
   
     13. The receiver according  claim 11 , wherein the delta sigma modulator is in the M-order structure. 
   
   
     14. The receiver according  claim 11 , wherein the demodulator comprises:
 a timing recovering unit that receives a clock that is L times the symbol clock generated by an oscillator, and the phase value, searches the phase value for a data decision timing with the resolution of 1/L of the symbol clock, and generates a phase detection request timing to operate the low-pass filter unit; and  
 a data deciding unit that decides reception data based on the phase value and the data decision timing, wherein  
 the low-pass filter unit operates at the phase detection request timing.  
 
   
   
     15. The receiver according to  claim 11 , further comprising a sample holding circuit unit that holds the amplified received baseband signal at a constant level during a predetermined second time, at a pre-stage of the delta sigma modulator. 
   
   
     16. A receiver comprising:
 a first quantizing unit that quantizes the phase of a received baseband signal;  
 a converting and selecting unit that linearly converts the received baseband signal based on a predetermined rule, and selectively outputs the signal after the linear conversion;  
 an integrating unit that integrates the output from the converting and selecting unit;  
 a second quantizing unit that quantizes the integration result by deciding the sign of the integration result based on the output from the first quantizing unit;  
 a delay unit that delays the output from the second quantizing unit by a predetermined time, and outputs the delayed signal to the convening and selecting unit;  
 an adding unit that adds the output from the first quantizing unit and the output from the second quantizing unit modulo the quantized value of the phase 2π;  
 a low-pass filter unit that sequentially latches phase values after the addition with internal shift registers, converts the whole data within the shift registers based on a predetermined rule when the phase values that cross over the quantized value of the phase 2π exist in the whole data, does not carry out the conversion when the phase values that cross over the quantized value of the phase 2π do not exist, averages the phase values in this state, and outputs the phase value after smoothing quantization noise; and  
 a demodulator that demodulates the reception data based on the phase value,  
 wherein the first quantizing unit, the converting and selecting unit, the integrating unit, the second quantizing unit, the delay unit, and the adding unit constitute a delta sigma modulator.  
 
   
   
     17. The receiver according  claim 16 , wherein differential inputs are applied to the first quantizing unit and the converting and selecting unit. 
   
   
     18. The receiver according  claim 16 , wherein the delta sigma modulator is in the M-order structure. 
   
   
     19. The receiver according  claim 16 , wherein the demodulator comprises:
 a timing recovering unit that receives a clock that is L times the symbol clock generated by an oscillator, and the phase value, searches the phase value for a data decision timing with the resolution of 1/L of the symbol clock, and generates a phase detection request timing to operate the low-pass filter unit; and  
 a data deciding unit that decides reception data based on the phase value and the data decision timing, wherein  
 the low-pass filter unit operates at the phase detection request timing.  
 
   
   
     20. The receiver according to  claim 16 , further comprising a sample holding circuit unit that holds the amplified received baseband signal at a constant level during a predetermined second time, at a pre-stage of the delta sigma modulator.