Semiconductor memory device having consistent skew over entire memory core

Abstract

A semiconductor memory device including a memory core, a data input circuit, a data output circuit, at least one data input/output line, at least one row control signal and at least one column control signal, wherein the data input circuit and the data output circuit are separately arranged, the memory core is positioned between the data input circuit and the data output circuit, the data input/output line extends from the data input circuit to the data output circuit across the memory core, and the row control signal line and the column control signal line simultaneously start from a first side of the data input circuit, proceed in along a side of the memory core to a corner of the memory core, the core being adjacent to the data output circuit, and then run from the corner to the opposite corner of the memory core.

1. A semiconductor memory device including a memory core, a data input circuit, a data output circuit, at least one data input/output line, at least one row control signal line and at least one column control signal line,
 wherein the data input circuit and the data output circuit are separately arranged, the memory core is positioned between the data input circuit and the data output circuit, the data input/output line extends from the data input circuit to the data output circuit across the memory core, and the row control signal line and the column control signal line start simultaneously from a first side of the data input circuit and proceed in parallel along a side of the memory core, and then run from the first side of the memory core to an opposite side of the memory core.  
 
   
   
     2. The semiconductor memory device according to  claim 1 , wherein the semiconductor memory device has the same skew over the entire memory core. 
   
   
     3. The semiconductor memory device according to  claim 1 , wherein a data input direction is the same as a direction of the row and column control signals. 
   
   
     4. The semiconductor memory device according to  claim 1 , wherein a data output direction is the same as a direction of the row and column control signals. 
   
   
     5. The semiconductor memory device according to  claim 1 , wherein a direction of a data storing control signal is the same as a direction of the row and column control signals.