Negative drop voltage generator in semiconductor memory device and method of controlling negative voltage generation

Abstract

In the negative drop voltage generating apparatus of a semiconductor memory device and the method of controlling a negative voltage generation. The apparatus generates a negative voltage having a level necessary for an operating mode in the semiconductor memory device. The apparatus includes a negative drop voltage generator having first and second output terminals and a voltage separated/integrated unit connected between the first and second output terminals of the negative drop voltage generator. The voltage separated/integrated unit performs a voltage separation and connection so that the negative voltages are generated with individually different levels or with the same level through the first and second output terminals, in response to an applied control signal.

1. A negative drop voltage generating apparatus in a semiconductor memory device, comprising:
 a negative drop voltage generator comprising a first output terminal and a second output terminal; and  
 a voltage separated/integrated unit connected between the first output terminal and the second output terminal of the negative drop voltage generator, wherein: 
 said voltage separated/integrated unit performs voltage separation or voltage connection depending on an applied control signal;  
 the first output terminal and the second output terminal output substantially the same voltage level if the voltage separated/integrated unit performs voltage connection; and  
 the first output terminal and the second output terminal output different voltage levels if the voltage separated/integrated unit performs voltage separation.  
 
 
   
   
     2. The apparatus as claimed in  claim 1 , wherein the second output terminal is connected to a negative voltage reception pad. 
   
   
     3. The apparatus as claimed in  claim 1 , wherein the applied control signal is applied through a mode register set in testing the semiconductor memory device. 
   
   
     4. A negative drop voltage generating apparatus in a semiconductor memory device, comprising:
 a first negative drop voltage generator comprising a first output terminal;  
 a second negative drop voltage generator comprising a second output terminal and connected to the first negative drop voltage generator; and  
 a voltage separated/integrated unit connected between the first output terminal and the second output terminal, wherein: 
 said voltage separated/integrated unit performs voltage separation or voltage connection depending on an applied control signal;  
 the first output terminal and the second output terminal output substantially the same voltage level if the voltage separated/integrated unit performs voltage connection; and  
 the first output terminal and the second output terminal output different voltage levels if the voltage separated/integrated unit performs voltage separation.  
 
 
   
   
     5. The apparatus as claimed in  claim 4 , wherein:
 the second negative drop voltage generator shares a detector provided within the first negative drop voltage generator; and  
 the second negative drop voltage generator generates a negative voltage higher than a level of negative voltage from the first negative drop voltage generator in a voltage separation operation.  
 
   
   
     6. The apparatus as claimed in  claim 5 , wherein the applied control signal is applied through a mode register set in testing the semiconductor memory device. 
   
   
     7. A negative drop voltage generating apparatus in a semiconductor memory device, comprising:
 a first negative drop voltage generator having a first output terminal;  
 a second negative drop voltage generator having a second output terminal; and  
 a voltage separated/integrated unit connected between the first output terminal and the second output terminal of the first and second negative drop voltage generators, wherein: 
 said voltage separated/integrated unit performs voltage separation or voltage connection depending on an applied control signal;  
 the first output terminal and the second output terminal output substantially the same voltage level if the voltage separated/integrated unit performs voltage connection; and  
 the first output terminal and the second output terminal output different voltage levels if the voltage separated/integrated unit performs voltage separation.  
 
 
   
   
     8. The apparatus as claimed in  claim 7 , wherein:
 the second negative drop voltage generator operates independently from the first negative drop voltage generator; and  
 the second negative drop voltage generator generates a negative voltage higher than a level of a negative voltage from the first negative drop voltage generator.  
 
   
   
     9. The apparatus as claimed in  claim 8 , wherein the applied control signal is applied through a mode register set in testing the semiconductor memory device. 
   
   
     10. The apparatus as claimed in  claim 7 , wherein the applied control signal is applied through a mode register set in testing the semiconductor memory device. 
   
   
     11. A method of controlling negative voltage generation during a specific operating mode in a semiconductor memory device having a negative drop voltage generator which has first and second output terminals, said method comprising:
 outputting different negative voltage levels from the first output terminal and the second output terminal, in response to a signal indicating the beginning of the specific operating mode; and  
 outputting substantially the same negative voltage level from the first output terminal and the second output terminal, in response to a signal indicating the end of the specific operating mode.  
 
   
   
     12. The method as claimed in  claim 11 , wherein the negative voltage necessary for the specific operating mode is received through a negative voltage pad from the outside of the device and is applied to a bulk region where cell transistors of the semiconductor memory device are formed. 
   
   
     13. The method as claimed in  claim 12 , wherein the signal indicating the beginning of the specific operating mode is applied through a mode register set in testing the semiconductor memory device. 
   
   
     14. A method of controlling negative voltage generation during a specific operating mode in a semiconductor memory device which comprises a first negative drop voltage generator having a first output terminal and a second negative drop voltage generator having a second output terminal, said method comprising:
 outputting different negative voltage levels from the first output terminal and the second output terminal, in response to a signal indicating the beginning of the specific operating mode; and  
 outputting substantially the same negative voltage levels from the first output terminal and the second output terminal, in response to a signal indicating the end of the specific operating mode.  
 
   
   
     15. The method as claimed in  claim 14 , wherein a level of the negative voltage generated through the first output terminal is lower than a level of the negative voltage generated through the second output terminal and is applied to a bulk region where cell transistors of the semiconductor memory device are formed. 
   
   
     16. The method as claimed in  claim 15 , wherein the signal indicating the beginning of the specific operating mode is a predetermined code signal applied through a mode register set in testing the semiconductor memory device.