Method and system for estimating microelectronic fabrication product yield

Abstract

Within a method for estimating a microelectronic fabrication product yield and a system for estimating the microelectronic fabrication product yield there is employed a specific mathematic algorithm for estimating yield of a new microelectronic fabrication product within at least one microelectronic fabrication facility. The specific algorithm is solved incident to parametric data correlation with existing production data within the at least one microelectronic fabrication facility.

1. A method for estimating a microelectronic fabrication product yield comprising:
 providing a database containing therein historic production data for production of a series of existing microelectronic fabrication products fabricated within at least one microelectronic fabrication facility, the historic production data comprising: 
 a series of historic die size options for the series of existing microelectronic fabrication products fabricated within the at least one microelectronic fabrication facility;  
 a series of arbitrarily determined historic mask complexity factors for a series of masks employed for fabricating the series of existing microelectronic fabrication products within the at least one microelectronic fabrication facility; and  
 a series of historic microelectronic fabrication product defect densities for the series of existing microelectronic fabrication products fabricated within the at least one microelectronic fabrication facility;  
 
 determining for a new microelectronic fabrication product to be fabricated within the at least one microelectronic fabrication facility: 
 a die size;  
 an N value which equals a summation of mask complexity factors for a series of masks employed for fabricating the new microelectronic fabrication as determined through correlation with the series of historic mask complexity factors; and  
 a Do value which is a baseline microelectronic fabrication product defect density determined through correlation with the series of historic microelectronic fabrication product defect densities; and  
 
 calculating an estimated yield for the new microelectronic fabrication product using the equation: 
     Est  Yield=1/(1+( Do *( resiX/ 25.4)*( resiY/ 25.4))) N    
 
 
     where resiX and resiY are chip's reference size X dimension and y dimension. 
   
   
     2. The method of  claim 1  wherein the new microelectronic fabrication product is selected from the group consisting of semiconductor integrated circuit microelectronic fabrications and ceramic substrate microelectronic fabrications. 
   
   
     3. The method of  claim 1  wherein the series of arbitrarily determined historic mask complexity factors span a range of from about 0 to about 1. 
   
   
     4. The method of  claim 1  wherein the series of arbitrarily determined historic mask complexity factors is determined employing a mask fabrication parameter selected from the group consisting of mask layer minimum linewidth dimensions, mask layer areal coverage and mask layer design complexity. 
   
   
     5. A method for estimating a semiconductor microelectronic fabrication product yield comprising:
 providing a database containing therein historic production data for production of a series of existing semiconductor microelectronic fabrication products fabricated within at least one microelectronic fabrication facility, the historic production data comprising: 
 a series of historic die size options for the series of existing semiconductor microelectronic fabrication products fabricated within the at least one semiconductor microelectronic fabrication facility;  
 a series of arbitrarily determined historic mask complexity factors for a series of masks employed for fabricating the series of existing semiconductor microelectronic fabrication products within the at least one semiconductor microelectronic fabrication facility; and  
 a series of historic semiconductor microelectronic fabrication product defect densities for the series of existing semiconductor microelectronic fabrication products fabricated within the at least one semiconductor microelectronic fabrication facility;  
 
 determining for a new semiconductor microelectronic fabrication product to be fabricated within the at least one semiconductor microelectronic fabrication facility: 
 a die size;  
 an N value which equals a summation of mask complexity factors for a series of masks employed for fabricating the new semiconductor microelectronic fabrication as determined through correlation with the series of historic mask complexity factors; and  
 a Do value which is a baseline semiconductor microelectronic fabrication product defect density determined through correlation with the series of historic semiconductor microelectronic fabrication product defect densities; and  
 
 calculating an estimated yield for the new semiconductor microelectronic fabrication product using the equation: 
     Est  Yield=1/(1+( Do *( resiX/ 25.4)*( resiY/ 25.4))) N    
 
 
     where resiX and resiY are chip's reference size X dimension and Y dimension. 
   
   
     6. The method of  claim 5  wherein the series of arbitrarily determined historic mask complexity factors span a range of from about 0 to about 1. 
   
   
     7. The method of  claim 5  wherein the series of arbitrarily determined historic mask complexity factors is determined employing a mask fabrication parameter selected from the group consisting of mask layer minimum linewidth dimensions, mask layer areal coverage and mask layer design complexity. 
   
   
     8. A system for estimating a microelectronic fabrication product yield comprising:
 a database containing therein historic production data for production of a series of existing microelectronic fabrication products fabricated within at least one semiconductor microelectronic fabrication facility, the historic production data comprising: 
 a series of historic die size options for the series of existing microelectronic fabrication products fabricated within the at least one microelectronic fabrication facility;  
 a series of arbitrarily determined historic mask complexity factors for a series of masks employed for fabricating the series of existing microelectronic fabrication products within the at least one microelectronic fabrication facility; and  
 a series of historic microelectronic fabrication product defect densities for the series of existing microelectronic fabrication products fabricated within the at least one microelectronic fabrication facility;  
 
 means for determining for a new microelectronic fabrication product to be fabricated within the at least one microelectronic fabrication facility: 
 a die size;  
 an N value which equals a summation of mask complexity factors for a series of masks employed for fabricating the new microelectronic fabrication as determined through correlation with the series of historic mask complexity factors; and  
 a Do value which is a baseline microelectronic fabrication product defect density determined through correlation with the series of historic microelectronic fabrication product defect densities; and  
 
 means for calculating an estimated yield for the new microelectronic fabrication product using the equation: 
     Est  Yield=1/(1+( Do *( resiX/ 25.4)*( resiY/ 25.4))) N    
 
 
     where resiX and resiY are chip's reference size X dimension and Y dimension. 
   
   
     9. The system of  claim 8  wherein the new microelectronic fabrication product is selected from the group consisting of semiconductor integrated circuit microelectronic fabrications and ceramic substrate microelectronic fabrications. 
   
   
     10. The system of  claim 8  wherein the series of arbitrarily determined historic mask complexity factors span a range of from about 0 to about 1. 
   
   
     11. The system of  claim 8  wherein the series of arbitrarily determined historic mask complexity factors is determined employing a mask fabrication parameter selected from the group consisting of mask layer minimum linewidth dimensions, mask layer areal coverage and mask layer design complexity. 
   
   
     12. A system for estimating a semiconductor microelectronic fabrication product yield comprising:
 a database containing therein historic production data for production of a series of existing semiconductor microelectronic fabrication products fabricated within at least one semiconductor microelectronic fabrication facility, the historic production data comprising: 
 a series of historic die size options for the series of existing semiconductor microelectronic fabrication products fabricated within the at least one semiconductor microelectronic fabrication facility;  
 a series of arbitrarily determined historic mask complexity factors for a series of masks employed for fabricating the series of existing semiconductor microelectronic fabrication products within the at least one semiconductor microelectronic fabrication facility; and  
 a series of historic semiconductor microelectronic fabrication product defect densities for the series of existing semiconductor microelectronic fabrication products fabricated within the at least one semiconductor microelectronic fabrication facility;  
 
 means for determining for a new semiconductor microelectronic fabrication product to be fabricated within the at least one semiconductor microelectronic fabrication facility: 
 a die size;  
 an N value which equals a summation of mask complexity factors for a series of masks employed for fabricating the new semiconductor microelectronic fabrication as determined through correlation with the series of historic mask complexity factors; and  
 a Do value which is a baseline semiconductor microelectronic fabrication product defect density determined through correlation with the series of historic semiconductor microelectronic fabrication product defect densities; and  
 
 means for calculating an estimated yield for the new semiconductor microelectronic fabrication product using the equation: 
     Est  Yield=1/(1+( Do *( resiX/ 25.4)*( resiY/ 25.4))) N    
 
 
     where resiX and resiY are chip's reference size X dimension and Y dimension. 
   
   
     13. The system of  claim 12  wherein the series of arbitrarily determined historic mask complexity factors span a range of from about 0 to about 1. 
   
   
     14. The system of  claim 12  wherein the series of arbitrarily determined historic mask complexity factors is determined employing a mask fabrication parameter selected from the group consisting of mask layer minimum linewidth dimensions, mask layer areal coverage and mask layer design complexity.