Signal processing device, signal processing method, delta-sigma modulation type fractional division PLL frequency synthesizer, radio communication device, delta-sigma modulation type D/A converter

Abstract

A fractional frequency divider ( 28 ) includes a latch ( 31 ) for holding frequency division data, a ΔΣ modulator ( 33 ), a digital dither circuit ( 32 ) for receiving a digital input F representing fraction part of the frequency division data from the latch ( 31 ) and supplying a digital output alternately changing between F+k and F−k (where k is an integer) or a F value itself to the ΔΣ modulator ( 33 ), and circuit means ( 34 through 38 ) for executing fractional frequency division based on integer part (M value) of the frequency division data and an output of the ΔΣ modulator ( 33 ). The digital dither circuit ( 32 ) is useful for suppressing a spurious signal generated as a result of concentration of quantization noise at a particular frequency when the ΔΣ modulator ( 33 ) receives a particular F value (e.g., F=2 n−1 ).

1. A signal processing device characterized by comprising:
 a delta-sigma modulator; and  
 a digital dither circuit, provided between the digital input and the delta-sigma modulator, for selectively supplying to the delta-sigma modulator a digital output which has been discretely changed from a digital input and of which a time average corresponds to the digital input or the digital input, according to a value for the digital input.  
 
     
     
       2. The signal processing device of  claim 1 , characterized in that the delta-sigma modulator supplies the digital output which has been discretely changed from the digital input and of which a time average corresponds to the digital input when the digital input is a particular value, and
 supplies the digital input to the delta-sigma modulator when the digital input is a value other than the particular value.  
 
     
     
       3. The signal processing device of  claim 1 , characterized in that the digital dither circuit supplies, as the digital output which has been discretely changed from the digital input and of which a time average corresponds to the digital input, a signal which periodically changes to F+k or F−k (where F is a value for the digital input and k is an integer) to the delta-sigma modulator. 
     
     
       4. The signal processing device of  claim 3 , characterized in that k is 1. 
     
     
       5. A signal processing method characterized in that when a given digital input is a particular value, a digital output which has been discretely changed from the digital input and of which a time average corresponds to the digital input is supplied to a delta-sigma modulator, and
 when the digital input is a value other than the particular value, the digital input is supplied to the delta-sigma modulator.  
 
     
     
       6. A delta-sigma modulation type fractional frequency division PLL frequency synthesizer which includes a phase locked loop (PLL) having a fractional frequency divider, the synthesizer characterized in that the fractional frequency divider includes
 a latch for holding given division data,  
 a delta-sigma modulator,  
 a digital dither circuit, provided between the latch and the delta-sigma modulator, for receiving a digital input representing fraction part of the frequency division data from the latch and selectively supplying to the delta-sigma modulator a digital output which has been discretely changed from the digital input and of which a time average corresponds to the digital output or the digital input, according to a value for the digital input, and  
 circuit means for executing a fractional frequency division based on integer part of the frequency division data and an output of the delta-sigma modulator.  
 
     
     
       7. The delta-sigma modulation type fractional frequency division PLL frequency synthesizer of  claim 6 , characterized in that the digital dither circuit includes
 a ½ frequency divider for generating a clock signal having a half frequency of a frequency of an output signal of the fractional frequency divider,  
 a first selector for alternately selecting, where an integral value is k, a positive constant value [+k] or a negative constant value [−k], in response to a logic level change of a clock signal from the ½ frequency divider,  
 an adder for adding a value for a digital input from the latch circuit and a constant value selected by the selector, and  
 a second selector for outputting a result from the addition by the adder when a value for a digital input from the latch circuit is a particular value and outputting a digital input from the latch circuit when a value of a digital input from the latch circuit is a value other than the particular value.  
 
     
     
       8. A radio communication device characterized by comprising the delta-sigma modulation type fractional frequency division PLL frequency synthesizer of  claim 6 . 
     
     
       9. A delta-sigma modulation type D/A converter characterized by comprising:
 a delta-sigma modulator;  
 a digital dither circuit, provided between the digital input and the delta-sigma modulator, for selectively supplying to the delta-sigma modulator a digital output which has been discretely changed from a digital input and of which a time average corresponds to the digital input or the digital input, according to a value for the digital input; and  
 filter means for removing quantization noise contained in an output of the delta-sigma modulator to obtain a desired analog output.