Method, system, and program for controlling multiple storage devices

Abstract

Provided are a method, system and article of manufacture for controlling one or more I/O devices coupled to a local bus. A local bus function is associated with the one or more I/O devices. A register corresponding to the local bus function is configured as a memory address. The one or more I/O devices are controlled via the configured register.

1. A method for controlling one or more I/O devices connected to a local bus, comprising:
 associating a local bus function with the one or more I/O devices;  
 if the one or more I/O devices are in a PCI IDE mode, configuring a register as an I/O address;  
 if the one or more I/O devices are in a direct access mode, configuring the resister corresponding to the local bus function as a memory address, wherein a switching is allowed between the PCI IDE mode and the direct access mode, wherein more than four I/O devices are capable of being controlled by using a single local bus function in the direct access mode, and wherein no more than four I/O device are capable of being controlled by using the single local bus function in the PCI IDE mode.  
 
   
   
     2. The method of  claim 1 , wherein the memory address is coupled to a memory space, wherein the memory space maps control to the one or more I/O devices, and wherein the one or more I/O devices are controlled by accessing the memory space. 
   
   
     3. The method of  claim 1 , wherein the register is configured as a memory base address register, and wherein the memory base address register is 32 bits or 64 bits long. 
   
   
     4. The method of  claim 1 , wherein the register is stored in a configuration header of the local bus function. 
   
   
     5. The method of  claim 1 , wherein the local bus is a PCI bus and the local bus function is a PCI function. 
   
   
     6. The method of  claim 1 , wherein the register is stored in a configuration header of the local bus function, and wherein the register is configured as a memory decoder by configuring the register as a memory base address register. 
   
   
     7. The method of  claim 1 , wherein the register is stored in a configuration header of the local bus function, and wherein the register is configured as a I/O decoder by configuring the register as a I/O base address register. 
   
   
     8. The method of  claim 1 , wherein in the direct access mode the one or more I/O devices are storage devices connected in a point-to-point mechanism to the local bus, wherein in the direct access mode the one or more I/O devices comply with the SATA interface, wherein in the direct access mode a SATA adapter is directly connected to the local bus, and wherein in the direct access mode the one or more I/O devices are greater than four in number and are capable of simultaneously performing I/O transactions through the SATA adapter. 
   
   
     9. A system, comprising:
 a local bus;  
 one or more I/O devices coupled to the local bus;  
 a local bus function associated with the one or more I/O devices, wherein the local bus function is a PCI function; and  
 a resister corresponding to the PCI function, wherein if the one or more I/O devices are in a PCI IDE mode the register is configured as in I/O address, and wherein if the one or more I/O devices are in a direct access mode the register is configured as a memory address, wherein a switching is allowed between the PCI IDE mode and the direct access mode, wherein more than four I/O devices are capable of being controlled by using a single local bus function in the direct access mode, and wherein no more than four I/O devices are capable of being controlled by using the single local bus function in the PCI IDE mode.  
 
   
   
     10. The system of  claim 9 , further comprising a host bus adapter, wherein the host bus adapter couples the one or more I/O devices to the local bus. 
   
   
     11. The system of  claim 9 , further comprising:
 a memory space, wherein the memory address is coupled to the memory space, wherein the memory space maps control to the one or more I/O devices, and wherein the one or more I/O devices are controlled by accessing the memory space.  
 
   
   
     12. The system of  claim 9 , wherein the register is configured as a memory base address register, and wherein the memory base address register is 32 bits or 64 bits long, and wherein the configured register functions as a programmable memory decoder. 
   
   
     13. The system of  claim 9 , further comprising:
 a configuration header coupled to the local bus function, wherein the register is stored in the configuration header, and wherein the register is configured as a memory decoder by configuring the register as a memory base address register.  
 
   
   
     14. The system of  claim 9 , further comprising:
 a configuration header coupled to the local bus function, wherein the register is stored in the local bus function, and wherein the register is configured as a I/O decoder by configuring the register as a I/O base address register.  
 
   
   
     15. The system of  claim 9 , wherein in the direct access mode the one or more I/O devices are storage devices connected in a point-to-point mechanism to the local bus, wherein in the direct access mode the one or more I/O devices comply with the SATA interface, wherein in the direct access mode a SATA adapter is directly connected to the local bus, and wherein in the direct access mode the one or more I/O devices are greater than four in number and are capable of simultaneously performing I/O transactions through the SATA adapter. 
   
   
     16. An article of manufacture for controlling one or more I/O devices connected to a local bus, wherein the article of manufacture is capable of causing operations, the operation comprising:
 associating a local bus function with the one or more I/O devices; if the one or more I/O devices are in a PCI IDE mode, configuring a register as an I/O address; and  
 if the one or more I/O devices are in a direct access mode, configuring the register corresponding to the local bus function as a memory address, wherein a switching is allowed between the PCI IDE mode and the direct access mode, wherein more than four I/O devices arc capable of being controlled by using a single local bus function in the direct access mode and wherein no more than four I/O devices are capable of being controlled by using the single local bus function in the PCI IDE mode.  
 
   
   
     17. The article of manufacture of  claim 16 , wherein the memory address is coupled to a memory space, wherein the memory space maps control to the one or more I/O devices, and wherein the one or more I/O devices are controlled by accessing the memory space, and wherein the configuring is performed by configuration software coupled to the local bus. 
   
   
     18. The article of manufacture of  claim 16 , wherein the configured register functions as a programmable memory decoder, wherein the register is configured as a memory base address register, and wherein the memory base address register is 32 bits or 64 bits long. 
   
   
     19. The article of manufacture of  claim 16 , wherein the register is stored in a configuration header of the local bus function, and wherein the register is configured as a memory decoder by configuring the register as a memory base address register. 
   
   
     20. The article of manufacture of  claim 16 , wherein the register is stored in a configuration header of the local bus function, and wherein the register is configured as a I/O decoder by configuring the register as a I/O base address register. 
   
   
     21. The article of manufacture of  claim 16 , wherein in the direct access mode the one or more I/O devices are storage devices connected in a point-to-point mechanism to the local bus, wherein in the direct access mode the one or more I/O devices comply with the SATA interface, wherein in the direct access mode a SATA adapter is directly connected to the local bus, and wherein in the direct access mode the one or more I/O devices are greater than four in number and are capable of simultaneously performing I/O transactions through the SATA adapter.