Semiconductor device

Abstract

A semiconductor device having a first circuit block supplied with a first operating voltage, a second circuit block supplied with a second operating voltage, a voltage generating circuit for generating a third operating voltage in response to the first operating voltage, and a third circuit block supplied with the third operating voltage. Preferably, the third operating voltage is generated such that the first operating voltage is increased to a fourth operating voltage by a voltage-up converter, and then the fourth operating voltage is dropped to the third operating voltage by a voltage down-converter. Hence, a power supply operating internally stably in spite of use of a relatively fluctuating voltage can be provided even in the case where a power-supply voltage is dropped.

1. A semiconductor device formed on a semiconductor chip comprising:
 a first circuit block supplied with a first operating voltage;  
 a second circuit block supplied with a second operating voltage lower than said first operating voltage;  
 a voltage generating circuit generating a third operating voltage in response to said first operating voltage; and  
 a third circuit block supplied with said third operating voltage;  
 wherein said voltage generating circuit includes a fourth circuit that outputs the third operating voltage which is a function of said first operating voltage, and a rate of a change of the third operating voltage to said first operating voltage varies from a first rate of change to a second rate of change greater than the first rate of change when said first operating voltage is higher than a first voltage.  
 
   
   
     2. The semiconductor device according to  claim 1 ,
 wherein said third operating voltage is lower than said first operating voltage.  
 
   
   
     3. The semiconductor device according to  claim 2 ,
 wherein said first voltage is a voltage higher than a voltage used for normal operation and wherein said fourth circuit controls the third operating voltage when an aging test is operated.  
 
   
   
     4. The semiconductor device according to  claim 2 ,
 wherein said third circuit block further includes a charge pump circuit and a regulator circuit;  
 wherein said charge pump circuit receives said first operating voltage and outputs a voltage inputted to said regulator circuit,  
 wherein said regulator circuit includes a plurality of diodes and a first transistor;  
 wherein said plurality of diodes are which is coupled in series between an output of said charge pump circuit and said source/drain path of said first transistor; and  
 wherein said third operating voltage is outputted from an output of said first transistor.  
 
   
   
     5. The semiconductor device according to  claim 4 ,
 wherein said plurality of diodes comprise a plurality of second transistors which have the same thickness of gate insulators of third transistors used in input and output circuits.  
 
   
   
     6. The semiconductor device according to  claim 5 ,
 wherein said second transistors are N type MOS transistors.  
 
   
   
     7. The semiconductor device according to  claim 4 ,
 wherein said third circuit block comprises a memory array having a plurality of DRAM memory cells.