Semiconductor memory cell

Abstract

A semiconductor memory cell includes a semiconductor substrate that defines a trench having trench walls. The semiconductor memory cell also includes a floating gate electrode positioned within the trench and insulated from the trench walls by a first insulation region; a control gate electrode surrounding the trench; and a second insulation layer on the surface of the semiconductor substrate. The semiconductor memory cell further includes a conductive layer positioned on the second insulation layer. The conductive layer includes a channel region positioned above the floating gate electrode. The semiconductor memory cell also includes a source region and a drain region. The source region and the drain region are each formed in the conductive layer. The source region and the drain region are also connected to the channel region.

1. A semiconductor memory cell, comprising:
 a semiconductor substrate defining a trench having trench walls;  
 a floating gate electrode positioned within the trench and insulated from the trench walls by a first insulation region;  
 a control gate electrode surrounding the trench;  
 a second insulaton layer on the surface of the semiconductor substrate;  
 a conductive layer positioned on the second insulation layer, the conductive layer comprising a channel region positioned above the floating gate electrode;  
 a source region formed in the conductive layer; and  
 a drain region formed in the conductive layer, the source region and the drain region being connected to the channel region.  
 
   
   
     2. The semiconductor memory cell of  claim 1 , wherein the control gate electrode comprises a doped region in the semiconductor substrate. 
   
   
     3. The semiconductor memory cell of  claim 1 , wherein the floating gate electrode comprises a polysilicon filling the trench. 
   
   
     4. The semiconductor memory cell of  claim 1 , wherein the conductive layer comprises an epitaxial layer of polysilicon. 
   
   
     5. The semiconductor memory cell of  claim 1 , further comprising:
 a first shallow trench isolation (STI) region formed in the semiconductor substrate; and a second STI region formed in the semiconductor substrate, the trench being between the first and second STI regions;  
 wherein the trenches isolate the semiconductor memory cell from other semiconductor memory cells.  
 
   
   
     6. The semiconductor memory cell of  claim 1 , wherein the control gate electrode encloses the floating gate electrode completely with the exception of the channel region at the surface. 
   
   
     7. A method of fabricating a memory cell on a semiconductor substrate, comprising:
 forming a trench within the semiconductor substrate, the trench having walls;  
 forming a first insulation layer on the trench walls;  
 forming a floating gate electrode in the trench and on the first insulation layer, the floating gate electrode being insulated from the trench walls by the first insulation layer;  
 forming a control gate electrode in the semiconductor substrate around the trench;  
 providing a second insulation layer on the surface of the semiconductor substrate;  
 providing a conductive layer on the second insulation layer, the conductive layer comprising a channel region positioned above the floating gate electrode;  
 forming a source region in the conductive layer; and  
 forming a drain region in the conductive layer, the source region and the drain region being connected to the channel region.  
 
   
   
     8. The method of  claim 7 , wherein forming the control gate electrode comprises reverse doping the semiconductor substrate. 
   
   
     9. The method of  claim 7 , wherein forming the floating gate electrode comprises filling the trench with polysilicon. 
   
   
     10. The method of  claim 7 , wherein forming the conductive layer comprises forming an epitaxial layer. 
   
   
     11. The method of  claim 7  further comprising: forming shallow trench isolation (STI) regions in the semiconductor substrate near the trench, the STI regions insulating the semiconductor memory cell from other semiconductor memory cells. 
   
   
     12. The method of  claim 7 , wherein forming a control gate electrode includes forming a control gate electrode such that the control gate electrode encloses the floating gate electrode completely with the exception of the channel region at the surface.