Clock supply circuit for supplying a processing clock signal used for processing an input signal having a predetermined frequency

Abstract

A clock supply circuit capable of supplying clock signals having different frequencies to processing circuits, simplifying the circuit configuration, and realizing a reduction of the power consumption only by using a low frequency external oscillator, wherein a reference clock is multiplied by a multiplication circuit to generate a multiplied clock, the multiplied clock is divided by a predetermined division ratio to generate a clock signal having a desired constant frequency by a receiving clock generating circuit, furthermore, a DSP clock generating circuit generates a clock signal having a variable frequency according to a processing load of a DSP in accordance with a judgment result of a load judgment circuit, so it is possible to supply a clock signal maintained synchronization with received signal as well as a clock signal having a frequency variably controlled in accordance with the processing load.

1. A clock supply circuit supplying a processing clock signal for processing an input signal having a predetermined frequency, said clock supply circuit comprising:
 a clock generating means generating a intermediate clock signal for processing said input signal, a first clock signal higher in frequency than the intermediate clock signal, and a second clock signal lower in frequency than the intermediate clock signal,  
 a clock switching means selecting any of the intermediate clock signal, the first clock signal or the second clock signal, supplying the selected one as said processing clock signal to the signal processing, and  
 a clock switching control means for processing said input signal with use of the selected processing clock signal, detecting an amount out-of-sync of the processing clock signal with respect to the input signal in accordance with the processing result, and controlling the clock switching in accordance with said detected amount out-of-sync,  
 wherein said clock generating means further comprises:  
 an oscillation means generating a reference clock signal having a predetermined reference frequency,  
 a multiplying means generating a multiplied clock signal obtained by multiplying said reference clock signal, and  
 
     a frequency division means for dividing said multiplied clock signal by different frequency division ratios to generate said intermediate clock signal, said first clock signal and said second clock signal, respectively, and
 wherein the clock switching means switches said clock signals using a predetermined time span as a switching time unit wherein at the start and ending time phases of said intermediate clock signal, said first and second clock signals match.  
 
   
   
     2. A clock supply circuit as set forth in  claim 1 , further comprises a counter for counting said multiplied clock signal, having a maximum count value set in accordance with a least common multiple of an intermediate division ration for generating said intermediate clock signal, a first division ratio for generating said first clock signal and a second division ratio for generating said second clock signal, wherein
 said clock switching means performs clock switching when the count value of said counter reaches a predetermined value.  
 
   
   
     3. A clock supply circuit as set forth in  claim 2 , wherein said predetermined value is zero or said maximum count value. 
   
   
     4. A clock supply circuit as set forth in  claim 1 , wherein
 said clock switching means switches said intermediate clock signal and said first clock signal using a predetermined time span as a first time switching unit wherein the start and ending time phases of said intermediate clock signal and said first clock signal match, and  
 switches intermediate clock signal and said second clock signal using a predetermined time span as a second time switching unit wherein the start and ending time phases of said intermediate clock signal and said second clock signal match.  
 
   
   
     5. A clock supply circuit as set forth in  claim 4 , further comprises
 a first counter counting said multiplied clock signal, having a first maximum count value set in accordance with a least common multiple of an intermediate division ratio for generating said intermediate clock signal and a first division ratio for generating said first clock signal, and  
 a second counter counting said multiplied clock signal, having a second maximum count value set in accordance with a least common multiple of a intermediate division ration for generating said intermediate clock signal and a second division ratio for generating said second clock signal, wherein  
 said clock switching means further comprises  
 a first switching circuit performing clock switching of the intermediate clock signal and the first clock signal when the count value of said first counter reaches a first value, and  
 a second switching circuit performing clock switching of the intermediate clock signal and the second clock signal when the count value of said second counter reaches a second value.  
 
   
   
     6. A clock supply circuit as set forth in  claim 5  wherein
 said first value is zero or said first maximum value, and said second value is zero or said second maximum value.  
 
   
   
     7. A clock supply circuit supplying a processing clock signal for processing an input signal having a predetermined frequency, said clock supply circuit comprising:
 a clock generating means generating a first clock signal and a second clock signal having a lower frequency than that of said first clock signal,  
 a clock switching means selecting any of the first clock signal or the second clock signal, supplying the selected one as said processing clock signal to the signal processing, and  
 a clock switching control means for processing said input signal with use of the selected processing clock signal, detecting an amount out-of-sync of the processing clock signal with respect to the input signal in accordance with the processing result, and controlling the clock switching in accordance with said detected amount out-of-sync,  
 wherein said clock generating means further comprises:  
 an oscillation means generating a reference clock signal having a predetermined reference frequency,  
 a multiplying means generating a multiplied clock signal obtained by multiplying said reference clock signal, and  
 a frequency division means for dividing said multiplied clock signal by different frequency division ratios to generate said first clock signal and said second clock signal, respectively, and wherein  
 the clock switching means switches said clock signals using a predetermined time span as a switching time unit wherein the start and ending time phases of said first and second clock signals match.  
 
   
   
     8. A clock supply circuit as set forth in  claim 7 , further comprises a counter for counting said multiplied clock signal, having a maximum count value set in accordance with a least common multiple of a first division ratio for generating said first clock signal and a second division ratio for generating said second clock signal, wherein
 said clock switching means performs clock switching when the count value of said counter reaches a predetermined value.  
 
   
   
     9. A clock supply circuit as set forth in  claim 8 , wherein said predetermined value is zero or said maximum count value.