Apparatus for filtering inter-node communication in a data processing system

Abstract

A method and system for communication in a system area network (SAN) data processing system are described. The SAN includes a plurality of interconnected nodes that each have at least one port for communication. To avoid communication-induced errors that may arise, for example, if multiple nodes share the same node ID, the port of a node in the SAN is marked as “fenced” to prevent transmission of packets of a first traffic type while permitting transmission of packets of a second traffic type. The marking of the port may be recorded, for example, in a configuration register of the port. While the port is fenced, only packets of other than the first traffic type are routed via the port. In one preferred embodiment, the second traffic type represents SAN configuration traffic, and the first traffic type represents non-configuration traffic. In this preferred embodiment, the marking of the port may be removed following communication of configuration traffic utilized to negotiate unique node ID throughout the SAN.

1. A network chip for a node in a system area network including a plurality of nodes, said network chip comprising:
 a port for inter-node communication;  
 means for marking the port to prevent transmission to another node of packets of a first traffic type while permitting transmission to another node of packets of a second traffic type, wherein said means for marking comprises means for marking said port by setting a port configuration register;  
 a routing table that associates said port with a node identifier of at least one of said plurality of nodes: and  
 means for, if said port is marked, routing via said port only packets not of said first traffic type, wherein said means for routing routes packets by reference to said routing table.  
 
   
   
     2. The network of  claim 1 , wherein said network chip comprises means for determining a traffic type of a packet by reference to a packet header of the packet. 
   
   
     3. A network chip for a node in a system area network including a plurality of nodes, said network chip comprising:
 a port for inter-node communication;  
 means for marking the port to prevent ant transmission to another node of packets of a first traffic type while permitting transmission to another node of packets of a second traffic type, wherein said first traffic type comprises non-configuration traffic and said second traffic type comprises configuration traffic;  
 means for, if said port is marked, routing via said port only packets not of said first traffic type; and  
 means for, following transmission of packets of configuration traffic, removing said marking of said port.  
 
   
   
     4. The network chip of  claim 3 , and further comprising means, responsive to transmission of said packets of configuration traffic, for altering a node identifier used in packet routing. 
   
   
     5. A network chip for a node in a system area network including a plurality of nodes, said network chip comprising:
 a port for inter-node communication;  
 means for marking the port to prevent transmission to another node of packets of a first traffic type while transmission to another node of packets of a second traffic type, wherein said means for marking comprises means for automatically marking said port if said port is unconnected at initialization of the system area network; and  
 means for, if said port is marked, routing via said port only packets not of said first traffic type.  
 
   
   
     6. A node for a system area network including a plurality of nodes, said node comprising:
 a processor;  
 a memory coupled to said processor; and  
 a network chip in accordance with  claim 1  coupled to said processor.  
 
   
   
     7. A system area network, comprising:
 a plurality of nodes; and  
 a network coupling said plurality of nodes for complication;  
 wherein a node among said plurality of nodes includes a network chip in accordance with  claim 1 .  
 
   
   
     8. A node for a system area network including a plurality of nodes, said node comprising:
 a processor,  
 a memory coupled to said processor, and  
 a network chip in accordance with  claim 3  coupled to said processor.  
 
   
   
     9. A system area network, comprising:
 a plurality of nodes; and  
 a network coupling said plurality of nodes for communication;  
 wherein a node among said plurality of nodes includes a network chip in accordance with  claim 3 .  
 
   
   
     10. A node for a system area network including a plurality of nodes, said node comprising:
 a processor;  
 a memory coupled to said processor, and  
 a network chip in accordance with  claim 5  coupled to said processor.  
 
   
   
     11. A system area network, comprising:
 a plurality of nodes; and  
 a network coupling said plurality of nodes for communication;  
 wherein a node among said plurality of nodes includes a network chip in accordance with  claim 5 .