Integrated circuit and circuit arrangement for converting a single-rail signal into a dual-rail signal

Abstract

An integrated circuit that converts a single rail signal into a dual-rail signal includes a clock signal connection, a data input to which a single-rail signal is applied, a data output on which a dual-rail signal is tapped off on output lines, and a converter, which is connected between the data input and the data output, that converts the single-rail signal into the dual-rail signal. The converter includes a memory cell having an input connected to the data input and output connections, wherein in a transparent state, the output connections provide the logically valid dual-rail signal, and a circuit arrangement, which is arranged between the output connections of the memory cell and the data output of the integrated circuit, that precharges the output lines connected to the output connections, and ensures a direct transition from a precharge phase to a logic state on the output lines, and vice versa.

1. An integrated circuit for converting a single-rail signal into a dual-rail signal, comprising:
 a clock signal connection for a clock signal;  
 a data input having an input line to which a single-rail signal is applied;  
 a data output on which a dual-rail signal is tapped off on output lines; and  
 a converter, which is connected between the data input and the data output, that converts the single-rail signal into the dual-rail signal, wherein the converter comprises:  
 a memory cell having an input connection connected to the data input on the integrated circuit and output connections, wherein in a transparent state, the output connections provide the dual-rail signal, which is logically valid; and  
 a circuit arrangement, which is arranged between the output connections of the memory cell and the data output of the integrated circuit, that precharges the output lines connected to the output connections, and ensures a direct transition from a precharge phase to a logic state on the output lines, and vice versa.  
 
     
     
       2. The integrated circuit as claimed in  claim 1 , wherein the output lines connected to the output connections are precharged after each falling or rising clock edge of the clock signal. 
     
     
       3. The integrated circuit as claimed in  claim 1 , wherein the clock signal is supplied to a first clock signal input on the memory cell. 
     
     
       4. The integrated circuit as claimed in  claim 1 , wherein the circuit arrangement has a cascode voltage switch logic section whose input connections are connected to the output connections of the memory cell and whose output connections are the output lines of the integrated circuit. 
     
     
       5. The integrated circuit as claimed in  claim 4 , wherein the circuit arrangement has a first and a second switching element whose control connections are respectively coupled to the clock signal and whose load paths are connected between a first supply potential connection and a respective one of the output lines connected to the output connections, with the first and second switching elements being in the transparent state of the memory cell. 
     
     
       6. The integrated circuit as claimed in  claim 4 , wherein the circuit arrangement has a first and a second switching element whose control connections are respectively coupled to the inverted clock signal and whose load paths are connected between a second supply potential connection and a respective one of the output lines connected to the output connections, with the first and second switching elements being in the transparent state of the memory cell. 
     
     
       7. The integrated circuit as claimed in  claim 1 , wherein the memory cell is a data latch. 
     
     
       8. A circuit arrangement having a plurality of integrated circuits as claimed in  claim 1 . 
     
     
       9. A circuit arrangement having a plurality of integrated circuits as claimed in  claim 2 . 
     
     
       10. A circuit arrangement having a plurality of integrated circuits as claimed in  claim 3 . 
     
     
       11. A circuit arrangement having a plurality of integrated circuits as claimed in  claim 4 . 
     
     
       12. A circuit arrangement having a plurality of integrated circuits as claimed in  claim 5 . 
     
     
       13. A circuit arrangement having a plurality of integrated circuits as claimed in  claim 6 . 
     
     
       14. A circuit arrangement having a plurality of integrated circuits as claimed in  claim 7 . 
     
     
       15. An integrated circuit for converting a single-rail signal into a dual-rail signal, comprising:
 a clock signal connection for a clock signal;  
 a data input having an input line to which a single-rail signal is applied;  
 a data output on which a dual-rail signal is tapped off on output lines; and  
 a converter, which is connected between the data input and the data output, that converts the single-rail signal into the dual-rail signal, wherein the converter comprises:  
 a memory cell having an input connection connected to the data input on the integrated circuit and output connections, wherein in a transparent state, the output connections provide the dual-rail signal, which is logically valid, and wherein an inverted data clock signal is supplied to a second clock signal input on the memory cell; and  
 a circuit arrangement, which is arranged between the output connections of the memory cell and the data output of the integrated circuit, that precharges the output lines connected to the output connections, and ensures a direct transition from a precharge phase to a logic state on the output lines, and vice versa.  
 
     
     
       16. A plurality of integrated circuits, wherein each of said integrated circuits converts a single-rail signal into a dual-rail signal, each of said integrated circuits comprising:
 a clock signal connection for a clock signal;  
 a data input having an input line to which a single-rail signal is applied;  
 a data output on which a dual-rail signal is tapped off on output lines; and  
 a converter, which is connected between the data input and the data output, that converts the single-rail signal into the dual-rail signal, wherein the converter comprises:  
 a memory cell having an input connection connected to the data input on the integrated circuit and output connections, wherein in a transparent state, the output connections provide the dual-rail signal, which is logically valid, and wherein an inverted data clock signal is supplied to a second clock signal input on the memory cell; and  
 a circuit arrangement, which is arranged between the output connections of the memory cell and the data output of the integrated circuit, that precharges the output lines connected to the output connections, and ensures a direct transition from a precharge phase to a logic state on the output lines, and vice versa.