Control clocks generator and method thereof for a high speed sense amplifier

Abstract

A control clocks generator and method thereof for a high speed sense amplifier generates control clocks by utilizing RC delay and gate delay, in combination with reference sensing delay induced from a reference sense amplifier, and thereby, is tracking well for the high speed sense amplifier with process, temperature and voltage variations.

1. A control clocks generator triggerred by an address transition pulse signal for a high speed sense amplifier, the generator comprising:
 a first RC delay apparatus for producing a precharge signal in response to the address transition pulse signal;  
 a second RC delay apparatus in combination with a first gate delay apparatus and a reference sensing delay apparatus for producing a latch signal in response to the address transition pulse signal; and  
 a second gate delay apparatus for producing a sense amplifier enable signal in response to the latch signal.  
 
   
   
     2. A generator according to  claim 1 , further comprising a third RC delay apparatus in combination with a third gate delay apparatus for producing a guard band for the latch signal in response to the precharge signal. 
   
   
     3. A generator according to  claim 2 , wherein the third RC delay apparatus is substantially same as the second RC delay apparatus. 
   
   
     4. A generator according to  claim 2 , wherein the third gate delay apparatus is substantially same as the first gate delay apparatus. 
   
   
     5. A generator according to  claim 1 , further comprising a third RC delay apparatus in combination with a third gate delay apparatus for producing a guard band for the latch signal in response to the address transition pulse signal. 
   
   
     6. A generator according to  claim 5 , wherein the third RC delay apparatus is substantially same as the second RC delay apparatus, and the third gate delay apparatus is substantially same as the first gate delay apparatus. 
   
   
     7. A generator according to  claim 1 , wherein the second RC delay apparatus is substantially same as the first RC delay apparatus. 
   
   
     8. A method for generating control clocks triggerred by an address transition pulse signal for a high speed sense amplifier, the method comprising the steps of:
 applying a first RC delay to the address transition pulse signal for producing a precharge signal;  
 applying a second RC delay, a first gate delay and a reference sensing delay to the address transition pulse signal for producing a latch signal; and  
 applying a second gate delay to the latch signal for producing a sense amplifier enable signal.  
 
   
   
     9. A method according to  claim 8 , further comprising applying a third RC delay and third gate delay to the precharge signal for producing a guard band for the latch signal. 
   
   
     10. A method according to  claim 8 , further comprising applying a third RC delay and third gate delay to the address transition pulse signal for producing a guard band for the latch signal. 
   
   
     11. A method according to  claim 8 , further comprising generating the reference sensing delay. 
   
   
     12. A method according to  claim 11 , further comprising sensing a mini-array for cell current simulation.