Three-transistor NAND and NOR gates for two-phase clock generators

Abstract

A two-phase non-overlapping clock generator ( 12 ) generating a sampling signal ( 20 ) utilizing a three transistor NAND gate ( 50 ). The NAND gate of the present invention eliminates one large PMOSFET ( 46 ), and has one NMOSFET ( 52 ) driven by the other phase and having its source grounded. The present invention yields substantial improvement on the jitter of the clock phases. Both rising and falling transitions are improved because of the greatly reduced self-loading of the NAND gate. Overshooting is eliminated, and the NAND gate body effect is minimized, providing enhanced jitter performance of the sampling signal and improving a signal to noise ratio (SNR). The principle of the present invention are also embodied in a NOR gate ( 70 ).

1. A circuit, comprising;
 a two-phase non-overlapping signal generator responsive to an external clock and generating a first phase and a second phase, the generator outputting a sampling signal at a sampling rate adapted to control a sampling device, the generator comprising a first NAND gate comprised of two NMOSFETs and only one PMOSFET.  
 
   
   
     2. The circuit as specified in  claim 1  wherein the first NAND gate is responsive to the external clock and the first phase. 
   
   
     3. The circuit as specified in  claim 1  wherein the generator comprises a first circuit portion generating the first phase and an identical second circuit portion generating the second phase, wherein the first NAND gate forms a portion of the second circuit portion. 
   
   
     4. The circuit as specified in  claim 1  wherein the generator comprises a first circuit portion including the first NAND gate and circuit portion further comprises at least two inverter gates, and a second circuit portion comprises a second NAND gate and at least two inverter gates. including an inverter gate responsively coupled to the first NAND gate. 
   
   
     5. The circuit as specified in  claim 1  wherein the generator further comprises an inverter gate, wherein the first NAND gate utilizes dynamic charge storage of the inverter gate for a limited interval of time. 
   
   
     6. The circuit as specified in  claim 5  wherein the first NAND gate has an output effectively insulated when utilizing the inverter gate dynamic charge. 
   
   
     7. The circuit as specified in  claim 5  wherein the inverter gate has a charge storage interval which is independent of the sampling rate. 
   
   
     8. The circuit as specified in  claim 6  wherein the charge storage interval is less than 300 ps. 
   
   
     9. The circuit as specified in  claim 6  wherein the charge storage interval is about 300-400 ps. 
   
   
     10. The circuit as specified in  claim 5  wherein the first NAND gate has approximately the same capacitive load as the inverter gate. 
   
   
     11. The circuit as specified in  claim 3  wherein one said NMOSFET has its source grounded and is driven by the first phase. 
   
   
     12. A two-phase non-overlapping clock generator generating a sampling signal, comprising:
 a first NAND gate receiving an external clock and serially coupled to at least a first inverter gate; and  
 a second NAND gate receiving the external clock and serially coupled to at least a second inverter gate, the first inverter gate being coupled to an input of the second NAND gate, wherein the second NAND gate is comprised of two NMOSFETS and only one PMOSFET.  
 
   
   
     13. The circuit as specified in  claim 12  wherein the second NAND gate reduces the loading effect on the first inverter gate as compared to a standard NAND gate having two PMOSFETS. 
   
   
     14. The circuit as specified in  claim 12  wherein the second NAND gate utilizes a dynamic charge storage of the second inverter gate for a limited interval of time. 
   
   
     15. The circuit as specified in  claim 14  wherein the second NAND gate has an output effectively insulated when utilizing the second inverter gate dynamic charge. 
   
   
     16. The circuit as specified in  claim 14  wherein the second inverter has a charge storage interval which is independent of the sampling rate. 
   
   
     17. The circuit as specified in  claim 16  wherein the charge storage interval is less than 300 ps. 
   
   
     18. The circuit as specified in  claim 16  wherein the charge storage interval is about 300-400 ps. 
   
   
     19. The circuit as specified in  claim 12  wherein the second NAND gate has approximately the same capacitive load as the second gate. 
   
   
     20. The circuit as specified in  claim 12  wherein the second NAND gate comprises two NMOSFETs and only one PMOSFET, wherein one of the NMOSFETs has its source grounded. 
   
   
     21. The circuit as specified in  claim 12  wherein said first NAND gate is serially coupled to a plurality of inverter gates. 
   
   
     22. The circuit as specified in  claim 21  wherein said second NAND gate is serially coupled to a plurality of inverter gates. 
   
   
     23. The circuit as specified in  claim 20  wherein the first inverter is coupled to the NMOSFET having its source grounded. 
   
   
     24. A two-phase non-overlapped clock generator generating a sample signal, comprising:
 a first NOR gate receiving the external clock and serially coupled to at least a first inverter gate;  
 a second NOR gate serially coupled to at least a second inverter gate, said first inverter gate being coupled to an input of the second NOR gate, wherein the second NOR gate is comprised of two PMOSFETS and only one NMOSFET.  
 
   
   
     25. The circuit as specified in  claim 24  wherein the first NOR gate is responsive to the external clock and the first phase. 
   
   
     26. The circuit as specified in  claim 24  wherein the generator comprises a first circuit portion generating the first phase and an identical second circuit portion generating the second phase, wherein the first NOR gate forms a portion of the second circuit portion. 
   
   
     27. The circuit as specified in  claim 24  wherein the generator comprises a first circuit portion including the first NOR gate and circuit portion further comprises at least two inverter gates, and a second circuit portion comprises a second NOR gate and at least two inverter gates. 
   
   
     28. The circuit as specified in  claim 24  further including an inverter gate responsively coupled to the first NOR gate. 
   
   
     29. The circuit as specified in  claim 28  wherein the generator further comprises an inverter gate, wherein the first NOR gate utilizes dynamic charge storage of the inverter gate for a limited interval of time. 
   
   
     30. The circuit as specified in  claim 28  wherein the first NOR gate has an output effectively insulated when utilizing the inverter gate dynamic charge. 
   
   
     31. The circuit as specified in  claim 28  wherein the inverter gate has a charge storage interval which is independent of the sampling rate. 
   
   
     32. The circuit as specified in  claim 30  wherein the charge storage interval is less than 300 ps. 
   
   
     33. The circuit as specified in  claim 30  wherein the charge storage interval is about 300-400 ps. 
   
   
     34. The circuit as specified in  claim 28  wherein the first NOR gate has approximately the same capacitive load as the inverter gate. 
   
   
     35. The circuit as specified in  claim 26  wherein one said PMOSPET has its source grounded and is driven by the first phase. 
   
   
     36. A two-phase non-overlapping clock generator generating a sampling signal comprising:
 a first NOR gate receiving an external clock and serially coupled to at least a first inverter gate; and  
 a second NOR gate receiving the external clock and serially coupled to at least a second inverter gate, the first inverter gate being coupled to an input of the second NOR gate, wherein the second NOR gate is comprised of two PMOSFETS and only one NMOSFET.  
 
   
   
     37. The circuit as specified in  claim 36  wherein the second NOR gate reduces the loading effect on the first inverter gate as compared to a standard NOR gate having two NMOSFETS. 
   
   
     38. The circuit as specified in  claim 36  wherein the second NOR gate utilizes a dynamic charge storage of the second inverter gate for a limited interval of time. 
   
   
     39. The circuit as specified in  claim 38  wherein the second NOR gate has an output effectively insulated when utilizing the second inverter gate dynamic charge. 
   
   
     40. The circuit as specified in  claim 38  wherein the second inverter has a charge storage interval which is independent of the sampling rate. 
   
   
     41. The circuit as specified in  claim 40  wherein the charge storage interval is less than 300 ps. 
   
   
     42. The circuit as specified in  claim 40  wherein the charge storage interval is about 300-400 ps. 
   
   
     43. The circuit as specified in  claim 36  wherein the second NOR gate has approximately the same capacitive load as the second gate. 
   
   
     44. The circuit as specified in  claim 36  wherein the second NOR gate comprises two PMOSFETs and only one NMOSFET, wherein one of the PMOSFETs has its source grounded. 
   
   
     45. The circuit as specified in  claim 36  wherein said first NOR gate is serially coupled to a plurality of inverter gates. 
   
   
     46. The circuit as specified in  claim 36  wherein said second NOR gate is serially coupled to a plurality of inverter gates. 
   
   
     47. The circuit as specified in  claim 44  wherein the first inverter is coupled to the PMOSFET having its source grounded.