Clock controlling method and circuit

Abstract

A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit 101 fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.

1. A clock control circuit comprising:
 a multi-phase clock generating circuit for generating and outputting first to nth clocks having respective difference phases from an input clock received and the size of the phase difference of the second through nth clocks is different than the size of the phase difference of the preceding clock, respectively;  
 a selector fed with said first to nth clocks to select and output one of said first to nth clocks; and  
 a control circuit fed with the input clock to generate a selection signal for selecting sequentially said first to nth clocks to provide the generated selection signal to said selector.  
 
     
     
       2. The clock control circuit as defined in  claim 1  wherein
 an output of the selection signal controlling selection of said selector is variably set by a mode signal input to said control circuit.  
 
     
     
       3. The clock control circuit as defined in  claim 1  wherein
 said multi-phase clock generating circuit comprises a multi-phase multiplication clock circuit for frequency dividing said input clock to generate multi-phase clocks to generate a signal by frequency multiplying said multi-phase clocks.  
 
     
     
       4. A clock control method comprising:
 generating first to Nth clocks of respective different phases (termed multi-phase clocks) from an input clock to provide the generated clocks to a selector and the size of the phase difference of the second through nth clocks is different than the size of the phase difference of the preceding clock, respectively and wherein  
 said selector sequentially selects and outputs said first to Nth clocks.