Multi-threaded processing of system management interrupts

Abstract

An information capturing technique captures information on a processor cycle that results in a high level interrupt, such as an SMI (System Management Interrupt). A memory controller is connected to at least one processor to control a memory in response to instructions from the at least one processor. An I/O controller is connected to the memory controller to control data flow to at least one device in response to instructions from the at least one processor. Lock down logic stores captured cycle information on a processor cycle that results in interrupt.

1. An apparatus comprising:
 a memory controller connected to at least one processor of a plurality of processors to control a memory in response to instructions from said at least one processor;  
 an I/O controller connected to said memory controller to control data flow to at least one device in response to instructions from said at least one processor; and  
 lock down logic to store captured cycle information of said processor cycle that results in a system management interrupt and to transfer the captured cycle information to each processor of said plurality of processors in response to said system management interrupt.  
 
   
   
     2. The apparatus of  claim 1 , the captured cycle information stored in the lock down logic comprising at least one of:
 an address of the processor cycle;  
 an indication as to whether the cycle was a READ or a WRITE cycle; and  
 an identity of said at least one processor which generated the processor cycle.  
 
   
   
     3. The apparatus of  claim 1 , wherein said lock down logic is disposed within one of:
 said memory controller;  
 said I/O controller; and  
 said at least one processor.  
 
   
   
     4. The apparatus of  claim 1 , said memory controller comprising a cycle decode to decode instructions from said at least one processor. 
   
   
     5. The apparatus of  claim 1 , said I/O controller comprising a cycle decode to decode instructions from said at least one processor. 
   
   
     6. The apparatus of  claim 1 , said I/O controller comprising an interrupt decode to decode said system management interrupt and output a system management interrupt signal to said at least one processor. 
   
   
     7. A method comprising:
 detecting a system management interrupt in response to decoding instructions from at least one processor of a plurality of processors;  
 outputting a system management interrupt signal to the at least one processor in response to the system management interrupt;  
 capturing and storing cycle information of a processor cycle that results in the system management interrupt, and  
 transferring at least a portion of the captured cycle information to each processor of the plurality of processors in response to the system management interrupt.  
 
   
   
     8. The method of  claim 7 , the stored captured cycle information comprising at least one of:
 an address of the processor cycle;  
 an indication as to whether the cycle was a READ or a WRITE cycle; and  
 an identity of the at least one processor which generated the processor cycle.  
 
   
   
     9. A method comprising:
 controlling a memory in response to instructions from at least one processor of a plurality of processors;  
 controlling data flow to at least one device in response to instructions from the at least one processor;  
 storing captured cycle information associated with a processor cycle that results in a system management interrupt; and  
 transferring at least a portion of the captured cycle information to each processor of the plurality of processors.  
 
   
   
     10. The method of  claim 9 , the captured stored cycle information comprising at least one of:
 an address of the processor cycle;  
 an indication as to whether the cycle was a READ or a WRITE cycle; and  
 an identity of the at least one processor which generated the processor cycle.  
 
   
   
     11. The method of  claim 9 , wherein the captured cycle information is stored within one of:
 a memory controller;  
 an I/O controller; and  
 the at least one processor.  
 
   
   
     12. The method of  claim 9 , further comprising decoding instructions from the at least one processor with the memory controller. 
   
   
     13. The method of  claim 9 , further comprising decoding instructions from the at least one processor with an I/O controller. 
   
   
     14. The method of  claim 9 , further comprising detecting a system management interrupt and outputting a system management interrupt signal to the at least one processor with an interrupt decode. 
   
   
     15. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method comprising:
 decoding instructions from at least one processor of a plurality of processors to decode a system management interrupt;  
 outputting a system management interrupt signal to the at least one processor in response to the decoded interrupt;  
 capturing and storing cycle information on a processor cycle that results in a system management interrupt; and  
 transferring at least a portion of the captured cycle information to each processor of the plurality of processors.  
 
   
   
     16. The program storage device of  claim 15 , the stored captured cycle information comprising at least one of:
 an address of the processor cycle;  
 an indication as to whether the cycle was a READ or a WRITE cycle; and  
 an identity of the at least one processor which generated the processor cycle.  
 
   
   
     17. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method comprising:
 controlling a memory in response to instructions from at least one processor of a plurality of processors;  
 controlling data flow to at least one device in response to instructions from the at least one processor;  
 storing captured cycle information associated with a processor cycle that results in a system management interrupt; and  
 transferring at least a portion of the captured cycle information to each processor of the plurality of processors.  
 
   
   
     18. The program storage device of  claim 17 , the stored captured cycle information comprising at least one of:
 an address of the processor cycle;  
 an indication as to whether the cycle was a READ or a WRITE cycle; and  
 an identity of the at least one processor which generated the processor cycle.  
 
   
   
     19. The program storage device of  claim 17 , wherein the captured cycle information is stored within one of:
 a memory controller;  
 an I/O controller; and  
 the at least one processor.  
 
   
   
     20. A method comprising
 determining that execution of an instruction by a processor of a plurality of processors results in a system management interrupt,  
 storing a processor identifier that identifies the processor that executed the instruction resulting in the system management interrupt,  
 sending a system management interrupt signal to each processor of the plurality of processors in response to the system management interrupt, and  
 in response to receiving the system management interrupt signal, executing a system management thread with the processor identified by the processor identifier.  
 
   
   
     21. The method of  claim 20  further comprising in response to receiving the system management interrupt signal, executing a thread other than the system management thread with a processor not identified by the processor identifier. 
   
   
     22. A method comprising
 determining that execution of an instruction by a processor of a plurality of processors results in a system management interrupt,  
 storing a processor identifier that identifies the processor that executed the instruction resulting in the system management interrupt, and  
 executing a thread other than a system management thread with a processor not identified by the processor identifier.  
 
   
   
     23. The method of  claim 22  further comprising executing the system management thread with the processor identified by the processor identifier. 
   
   
     24. A system for a plurality of processors comprising
 an interrupt decoder to generate a system management interrupt signal in response to an instruction executed by a processor of the plurality of processors, and  
 logic to store a processor identifier for the processor that executed the instruction resulting in the system management interrupt, wherein  
 the interrupt decoder provides each processor of the plurality of processors with the system management interrupt signal, and  
 wherein a processor in response to the system management interrupt signal executes a system management thread if identified by the processor identifier of the logic and does not execute the system management thread if not identified by the processor identifier of the logic.  
 
   
   
     25. The system of  claim 24  wherein the interrupt decoder instructs the logic to store the processor identifier. 
   
   
     26. The system of  claim 24  wherein each processor of the plurality of processors in response to the system management interrupt signal determines whether the processor identifier of the logic identifies the processor. 
   
   
     27. A method comprising
 simultaneously executing a first thread and a second thread with a processor, and  
 simultaneously executing the second thread and a system management thread with the processor in response to determining that execution of the first thread caused a system management interrupt.  
 
   
   
     28. The method of  claim 27  further comprises
 suspending execution of the first thread with the processor to execute a system management interrupt handler in response to the system management interrupt, and  
 invoking execution of the system management thread with the processor in response to the system management interrupt handler determining that the first thread caused the system management interrupt.  
 
   
   
     29. The method of  claim 27  further comprising
 suspending execution of the second thread with the processor to execute a system management interrupt handler with the processor in response to the system management interrupt, and  
 resuming execution of the second thread with the processor in response to the system management interrupt handler determining that execution of the second thread with the processor did not cause the system management interrupt.  
 
   
   
     30. The method of  claim 27  further comprising
 executing a third thread with another processor,  
 suspending execution of the third thread with the another processor to execute a system management interrupt handler with the another processor in response to the system management interrupt, and  
 resuming the execution of the third thread with the another processor in response to the system management interrupt handler determining that the execution of the third thread with the another processor did not cause the system management interrupt.