Techniques for automatic eye-degradation testing of a high-speed serial receiver

Abstract

Embodiments of the invention relate to techniques for automatic degradation testing of a high-speed serial receiver. A transmitter manipulator couples to a transmitter of a serial interface circuit. The transmitter is coupled to the receiver of the serial interface circuit. The transmitter manipulator includes a storage to store one of current compensation values or impedance compensation values and sequencing logic to dynamically sequence the one of the current compensation values or impedance compensation values to the transmitter. The transmitter responsive to the dynamically sequenced one of the current or impedance compensation values generates a degraded test pattern signal to transmit to the receiver in order to test the receiver.

1. An apparatus comprising:
 a transmitter manipulator to couple to a transmitter of a serial interface circuit, the transmitter to couple to a receiver of the serial interface circuit, the transmitter manipulator further including,
 a storage to store one of current compensation values or impedance compensation values, and 
 sequencing logic to dynamically sequence the one of the current compensation values or impedance compensation values to the transmitter; 
 
 wherein the transmitter responsive to the dynamically sequenced one of the current or impedance compensation values generates a degraded test pattern signal to transmit to the receiver in order to test the receiver. 
 
   
   
     2. The apparatus of  claim 1 , wherein, the degraded test pattern signal forms an eye-shaped degraded test pattern signal. 
   
   
     3. The apparatus of  claim 1 , wherein, the storage comprises a register array. 
   
   
     4. The apparatus of  claim 1 , wherein, the current compensation values are coupled to a current compensation circuit of the transmitter. 
   
   
     5. The apparatus of  claim 1 , wherein, the impedance compensation values are coupled to an impedance compensation circuit of the transmitter. 
   
   
     6. The apparatus of  claim 1 , wherein, the storage comprises:
 a current compensation value storage to store the current compensation values; and 
 an impedance compensation value storage to store the impedance compensation values. 
 
   
   
     7. The apparatus of  claim 6 , wherein, the sequencing logic is to dynamically sequence the current compensation values and the impedance compensation values to the transmitter, wherein the transmitter responsive to the dynamically sequenced current and impedance compensation values generates a degraded test pattern signal to transmit to the receiver in order to test the receiver. 
   
   
     8. The apparatus of  claim 7 , wherein, the degraded test pattern signal forms an eye-shaped degraded test pattern signal. 
   
   
     9. The apparatus of  claim 7 , wherein, the current compensation value storage and the impedance compensation value storage each comprise register arrays, respectively. 
   
   
     10. The apparatus of  claim 7 , wherein, the current compensation values are coupled to a current compensation circuit of the transmitter. 
   
   
     11. The apparatus of  claim 7 , wherein, the impedance compensation values are coupled to an impedance compensation circuit of the transmitter. 
   
   
     12. The apparatus of  claim 7 , further comprising a comparator, the comparator to compare the degraded test pattern signal transmitted to the receiver by the transmitter to a received test pattern signal received by the receiver in order to test the receiver. 
   
   
     13. A method comprising:
 storing one of current compensation values or impedance compensation values; 
 dynamically sequencing the one of the current compensation values or impedance compensation values to a transmitter of a serial interface circuit; 
 generating a degraded test pattern signal based on the dynamically sequenced one of the current compensation values or impedance compensation values; and 
 transmitting the degraded test pattern signal to a receiver of the serial interface circuit in order to test the receiver. 
 
   
   
     14. The method of  claim 13 , wherein, the degraded test pattern signal forms an eye-shaped degraded test pattern signal. 
   
   
     15. The method of  claim 13 , further comprising, coupling the current compensation values to a current compensation circuit of the transmitter. 
   
   
     16. The method of  claim 13 , further comprising, coupling the impedance compensation values to an impedance compensation circuit of the transmitter. 
   
   
     17. The method of  claim 13 , wherein, storing one of current compensation values or impedance compensation values, further comprises, storing both the current compensation values and the impedance compensation values. 
   
   
     18. The method of  claim 17 , further comprising,
 dynamically sequencing both of the current compensation values and the impedance compensation values to the transmitter to generate a degraded test pattern signal; and 
 transmitting the degraded test pattern signal to the receiver in order to test the receiver. 
 
   
   
     19. The method of  claim 18 , wherein, the degraded test pattern signal forms an eye-shaped degraded test pattern signal. 
   
   
     20. The method of  claim 18 , further comprising, comparing the degraded test pattern signal transmitted to the receiver by the transmitter to a received test pattern signal received by the receiver in order to test the receiver. 
   
   
     21. A serial interface circuit comprising:
 a transmitter; 
 a receiver; 
 a transmitter manipulator to couple to the transmitter, the transmitter to couple to the receiver, the transmitter manipulator further including,
 a storage to store one of current compensation values or impedance compensation values, and 
 sequencing logic to dynamically sequence the one of the current compensation values or impedance compensation values to the transmitter; 
 
 wherein the transmitter responsive to the dynamically sequenced one of the current or impedance compensation values generates a degraded test pattern signal to transmit to the receiver in order to test the receiver. 
 
   
   
     22. The serial interface circuit of  claim 21 , wherein, the degraded test pattern signal forms an eye-shaped degraded test pattern signal. 
   
   
     23. The serial interface circuit of  claim 21 , wherein, the storage comprises a register array. 
   
   
     24. The serial interface circuit of  claim 21 , wherein, the current compensation values are coupled to a current compensation circuit of the transmitter. 
   
   
     25. The serial interface circuit of  claim 21 , wherein, the impedance compensation values are coupled to an impedance compensation circuit of the transmitter. 
   
   
     26. The serial interface circuit of  claim 21 , wherein, the storage comprises:
 a current compensation value storage to store the current compensation values; and 
 an impedance compensation value storage to store the impedance compensation values. 
 
   
   
     27. The serial interface circuit of  claim 26 , wherein, the sequencing logic is to dynamically sequence the current compensation values and the impedance compensation values to the transmitter, wherein the transmitter responsive to the dynamically sequenced current and impedance compensation values generates a degraded test pattern signal to transmit to the receiver in order to test the receiver. 
   
   
     28. The serial interface circuit of  claim 27 , wherein, the degraded test pattern signal forms an eye-shaped degraded test pattern signal. 
   
   
     29. The serial interface circuit of  claim 27 , wherein, the current compensation value storage and the impedance compensation value storage each comprise register arrays, respectively. 
   
   
     30. The serial interface circuit of  claim 27 , wherein, the current compensation values are coupled to a current compensation circuit of the transmitter. 
   
   
     31. The serial interface circuit of  claim 27 , wherein, the impedance compensation values are coupled to an impedance compensation circuit of the transmitter. 
   
   
     32. The serial interface circuit of  claim 27 , further comprising a comparator, the comparator to compare the degraded test pattern signal transmitted to the receiver by the transmitter to a received test pattern signal received by the receiver in order to test the receiver. 
   
   
     33. The serial interface circuit of  claim 27  being coupled to a chipset of a computer system. 
   
   
     34. The serial interface circuit of  claim 33 , wherein, the chipset includes a Memory Control Hub (MCH) and an Input/Output Control Hub (ICH), the serial interface being coupled to the ICH. 
   
   
     35. The serial interface circuit of  claim 33 , wherein, the chipset is coupled to a processor by a Front-Side Bus (FSB).