Structure and method for fabricating semiconductor structures and devices utilizing piezoelectric materials

Abstract

High quality epitaxial layers of piezoelectric monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the piezoelectric monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying piezoelectric monocrystalline material layer.

We claim:  
     
       1. A semiconductor structure comprising:
 a monocrystalline silicon substrate;  
 an amorphous oxide material in contact with the monocrystalline silicon substrate;  
 a monocrystalline metal oxide overlying the amorphous oxide material;  
 a metal capping layer in contact with said metal oxide;  
 a compound semiconductor template layer in contact with said capping layer; and;  
 a monocrystalline compound semiconductor material in contact with said template layer,  
 wherein the monocrystalline compound semiconductor material is piezoelectric, and wherein the monocrystalline compound semiconductor material thickness is between about 0.5 μm and 10 μm.  
 
     
     
       2. The semiconductor structure of  claim 1  further comprising at least one conductive element in contact with the monocrystalline compound semiconductor material. 
     
     
       3. The semiconductor structure of  claim 1  wherein the monocrystalline compound semiconductor material is selected from the group consisting of gallium arsenide and aluminum gallium arsenide. 
     
     
       4. A semiconductor structure comprising:
 a monocrystalline silicon substrate;  
 an amorphous oxide material in contact with the monocrystalline silicon substrate;  
 a monocrystalline metal oxide overlying the amorphous oxide material;  
 a metal capping layer in contact with said metal oxide;  
 a compound semiconductor template layer in contact with said capping layer; and;  
 a monocrystalline compound semiconductor material in contact with said template layer, wherein the monocrystalline compound semiconductor material is piezoelectric, and  
 wherein the monocrystalline compound semiconductor material creates a reflective surface.  
 
     
     
       5. The semiconductor structure of  claim 4  further comprising at least one conductive element in contact with the monocrystalline compound semiconductor material. 
     
     
       6. The semiconductor structure of  claim 4  wherein the monocrystalline compound semiconductor material is selected from the group consisting of gallium arsenide and aluminum gallium arsenide. 
     
     
       7. The semiconductor structure of  claim 4  wherein the monocrystalline compound semiconductor material thickness is between about 0.05 μm and 100 μm. 
     
     
       8. The semiconductor structure of  claim 4  further comprising an integrally formed electrical component in communication with the reflective surface of the monocrystalline compound semiconductor material. 
     
     
       9. A semiconductor structure comprising:
 a monocrystalline silicon substrate;  
 an amorphous oxide material in contact with the monocrystalline silicon substrate;  
 a monocrystalline metal oxide overlying the amorphous oxide material;  
 a metal capping layer in contact with said metal oxide;  
 a compound semiconductor template layer in contact with said capping layer; and;  
 a monocrystalline compound semiconductor material in contact with said template layer, wherein the monocrystalline compound semiconductor material is piezoelectric,  
 further comprising a reflective material overlying the monocrystalline compound semiconductor material.  
 
     
     
       10. The semiconductor structure of  claim 9  further comprising at least one conductive element in contact with the monocrystalline compound semiconductor material. 
     
     
       11. The semiconductor structure of  claim 9  wherein the monocrystalline compound semiconductor material is selected from the group consisting of gallium arsenide and aluminum gallium arsenide. 
     
     
       12. The semiconductor structure of  claim 9  wherein the monocrystalline compound semiconductor material thickness is between about 0.05 μm and 100 μm. 
     
     
       13. The semiconductor structure of  claim 9  further comprising an integrally formed electrical component in communication with the reflective material overlying the monocrystalline compound semiconductor material. 
     
     
       14. A semiconductor structure comprising:
 a monocrystalline silicon substrate;  
 an amorphous oxide material in contact with the monocrystalline silicon substrate;  
 a monocrystalline metal oxide overlying the amorphous oxide material;  
 a metal capping layer in contact with said metal oxide;  
 a compound semiconductor template layer in contact with said capping layer;  
 a monocrystalline compound semiconductor material in contact with said template layer, and  
 a piezoelectric material overlying the monocrystalline compound semiconductor material  
 wherein the piezoelectric material is selected from the group consisting of piezoelectric monocrystalline semiconductor material and piezoelectric monocrystalline ceramic material,  
 wherein the piezoelectric monocrystalline semiconductor material is selected from the group consisting of gallium arsenide and aluminum gallium arsenide, and  
 wherein the piezoelectric monocrystalline semiconductor material thickness is between about 0.05 μm and 10 μm.  
 
     
     
       15. A semiconductor structure comprising:
 a monocrystalline silicon substrate;  
 an amorphous oxide material in contact with the monocrystalline silicon substrate;  
 a monocrystalline metal oxide overlying the amorphous oxide material;  
 a metal capping layer in contact with said metal oxide;  
 a compound semiconductor template layer in contact with said capping layer;  
 a monocrystalline compound semiconductor material in contact with said template layer, and  
 a piezoelectric material overlying the monocrystalline compound semiconductor material  
 wherein the piezoelectric material is selected from the group consisting of piezoelectric monocrystalline semiconductor material and piezoelectric monocrystalline ceramic material,  
 wherein the piezoelectric monocrystalline ceramic material is selected from the group consisting of barium titanate, lead titanate, potassium niobate, lead niobate, and lead zirconate titanate, and  
 wherein the piezoelectric monocrystalline semiconductor material thickness is between about 0.5 μm and 200 μm.  
 
     
     
       16. The semiconductor structure of  claim 15  wherein the piezoelectric ceramic material thickness is between about 5 μm and 25 μm. 
     
     
       17. A semiconductor structure comprising:
 an amorphous oxide material in contact with the monocrystalline silicon substrate;  
 a monocrystalline metal oxide overlying the amorphous oxide material;  
 a metal capping layer in contact with said metal oxide;  
 a compound semiconductor template layer in contact with said capping layer;  
 a monocrystalline compound semiconductor material in contact with said template layer; and  
 a piezoelectric material overlying the monocrystalline compound semiconductor material  
 wherein the piezoelectric material creates a reflective surface.  
 
     
     
       18. A semiconductor structure comprising:
 a monocrystalline silicon substrate;  
 an amorphous oxide material in contact with the monocrystalline silicon substrate;  
 a monocrystalline metal oxide overlying the amorphous oxide material;  
 a metal capping layer in contact with said metal oxide;  
 a compound semiconductor template layer in contact with said capping layer;  
 a monocrystalline compound semiconductor material in contact with said template layer, and  
 a piezoelectric material overlying the monocrystalline compound semiconductor material,  
 further comprising a reflective material overlying the piezoelectric material.  
 
     
     
       19. The semiconductor structure of  claim 17  further comprising an integrally formed electrical component in communication with the reflective surface of the piezoelectric material. 
     
     
       20. The semiconductor structure of  claim 18  further comprising an integrally formed electrical component in communication with the reflective material overlying the piezoelectric material.