Symbol combining device for multi-path diversity
Abstract
A symbol combining device for multi-path diversity includes a plurality of demodulation circuits for demodulating received signals, a common memory for storing outputs of the demodulation circuits, a symbol combiner for receiving the outputs of the common memory corresponding to the demodulation circuits and for combining the outputs, and a memory controller for controlling the common memory to timely separate the write and read operations. To timely separate the write and read operations, the memory controller controls the common memory in order that the demodulation circuits sequentially access the common memory and the resultant outputs of the demodulation circuits are written in the common memory, and the symbol combiner reads the outputs of the demodulation circuits written in the common memory sequentially. Because the deskewer of the symbol combining device is constructed of a single memory, not FIFO by channels, the required number of gates is about 40% of the FIFO by channels, and the size of the symbol combining device is reduced to 40%. Further, the symbol combining device can be easily adaptable to change of the number of channels for various services.
Claims
exact text as granted — not AI-modified1. A symbol combining device for multi-path diversity comprising:
a plurality of demodulation circuit for demodulating received signals, wherein each demodulation circuit demodulates the received signals of different channels;
a common memory for storing outputs of the demodulation circuits;
a symbol combiner for receiving the outputs of the common memory corresponding to the demodulation circuits and for combining the outputs of the common memory; and
a memory controller for controlling the write and read operations of the common memory to timely separate the write and read operations;
wherein, in contiguous write and read operations, the outputs of the demodulation circuits written in the common memory and the outputs of the demodulation circuits read from the common memory are signals provided to the symbol combiner in a predetermined time difference distinguishing the different channels.
2. The device of claim 1 , wherein the demodulation circuits sequentially access the common memory, the outputs of the demodulation circuits are written in the common memory, and the symbol combiner reads the outputs of the demodulation circuits written in the common memory sequentially.
3. The device of claim 1 , wherein the memory controller instructs the number of the demodulation circuits in accordance with receipt conditions.
4. The device of claim 1 , wherein the memory controller instructs the number of the demodulation circuits accessing sequentially to the common memory in response to channel configuration signals determining the number of channels.
5. The device of claim 1 , wherein the common memory is composed of a single memory.
6. The device of claim 1 , wherein the common memory is composed of a number of memories smaller than the number of channels.
7. The device of claim 1 , wherein the write and read operations for each channel are performed at the speed of a main clock of the symbol combining device.
8. The device of claim 1 , wherein the read operation is carried out immediately after the write operation.
9. A mobile station for wireless communication having a symbol combining device, wherein the symbol combining device comprises:
a plurality of demodulation circuits for demodulating received signals, wherein each demodulation circuit demodulates the received signals of different channels;
a common memory for storing outputs of the demodulation circuits;
a symbol combiner for receiving the outputs of the common memory corresponding to the demodulation circuits and for combining the outputs of the common memory; and
a memory controller for controlling the common memory to timely separate the write and read operations;
wherein, in contiguous write and read operations, the outputs of the demodulation circuits written in the common memory and the output of the demodulation circuits read from the common memory are signals provided to the symbol combiner in a predetermined time difference distinguishing the different channels.
10. The mobile station of claim 9 , wherein the demodulation circuits sequentially access the common memory, and the resultant outputs of the demodulation circuits are written in the common memory, and the symbol combiner reads the outputs of the demodulation circuits written in the common memory sequentially.
11. The mobile station of claim 9 , wherein the memory controller instructs the number of demodulation circuits accessing sequentially to the common memory in response to channel configuration signals determining the number of channels.
12. The mobile station of claim 9 , wherein the common memory is composed of a number of memories smaller than the number of channels.
13. The mobile station of claim 9 , wherein the write and read operations for each channel are performed at the speed of a main clock of the symbol combining device.
14. The mobile station of claim 9 , wherein the read operation is carried out immediately after the write operation.
15. A symbol combining device for multi-path diversity comprising:
a plurality of demodulation circuits for demodulating received signals, wherein each demodulation circuit demodulates the received signals of different channels;
a common memory for storing outputs of the demodulation circuits;
a symbol combiner for receiving the outputs of the common memory corresponding to the demodulation circuits and for combining the outputs of the common memory; and
a memory controller for controlling the write and read operations of the common memory to timely separate the write and read operations;
wherein the memory controller instructs the number of the demodulation circuits accessing sequentially to the common memory in response to channel configuration signals determining the number of channels.
16. A mobile station for wireless communication having a symbol combining device, wherein the symbol combining device comprises:
a plurality of demodulation circuits for demodulating received signals, wherein each demodulation circuit demodulates the received signals of different channels;
a common memory for storing outputs of the demodulation circuits;
a symbol combiner for receiving the outputs of the common memory corresponding to the demodulation circuits and for combining the outputs of the common memory; and
a memory controller for controlling the common memory to timely separate the write and read operations;
wherein the memory controller instructs the number of demodulation circuits accessing sequentially to the common memory in response to channel configuration signals determining the number of channels.Cited by (0)
No later patents cite this yet.
References (0)
No backward citations on record.