Switched-capacitor circuit with scaled reference voltage

Abstract

A pipelined analog-to-digital converter (ADC) ( 30 ) with improved precision is disclosed. The pipelined ADC ( 30 ) includes a sequence of stages ( 20 ), each of which includes a sample-and-hold circuit ( 22 ), an analog-to-digital converter ( 23 ), and the functions of a digital-to-analog converter (DAC) ( 25 ), an adder ( 24 ), and a gain stage ( 27 ) at which a residue signal (RES) is generated for application to the next stage ( 20 ) in the sequence. A multiplying DAC ( 28 ) performs the functions of the DAC ( 25 ), adder ( 24 ), and gain stage ( 27 ) in the stage ( 20 ), and is based on an operational amplifier ( 29 ). Sample capacitors (C 10 , C 20 ) and reference capacitors (C 12 2 , C 22 2 ) receive the analog input from the sample-and-hold circuit ( 22 ) in a sample phase; parallel capacitors (C 12 1 , C 22 1 ) are provided to maintain constant circuit gain. Extended reference voltages (V REFPX, V REFNX ) at levels that exceed the output range (V 0 +, V 0 −) of the operational amplifier ( 29 ) are applied to the reference capacitors, in response to the digital output of the analog-to-digital converter ( 23 ) in its stage ( 20 ). The reference capacitors (C 12 , C 22 ) are scaled according to the extent to which the extended reference voltages (V REFPX, V REFNX ) exceed the op amp output levels (V 0 +, V 0 −). The effects of noise on the reference voltages (V REFPX, V REFNX ) on the residue signal (RES) are thus greatly reduced.

1. A multiplying digital-to-analog converter (DAC), comprising:
 an operational amplifier, having first and second inputs, and having an output driving a signal over an output range between first and second output level voltages responsive to signals received at the first and second inputs; 
 a first sampling capacitor circuit, comprising a first sample capacitor, for receiving an input voltage and storing the input voltage at the first sample capacitor in a first clock phase, the first sampling capacitor circuit having an output coupled to a first input of the operational amplifier; 
 a first feedback switch, connected between the output of the operational amplifier and the first sample capacitor, for connecting the first sample capacitor in a feedback loop in a second clock phase; and 
 a first reference capacitor circuit, comprising:
 a first reference capacitor, coupled to the first input of the operational amplifier; 
 a first parallel capacitor, coupled to the first input of the operational amplifier; 
 clocked switches, for coupling the input voltage to the first reference capacitor and the first parallel capacitor in the first clock phase; and 
 
 switch circuitry, for receiving a reference voltage that exceeds the first output level voltage by a factor, and for charging the first reference capacitor with the reference voltage in the second clock phase, the first reference capacitor having a capacitance less than a capacitance of the first sample capacitor by the factor. 
 
   
   
     2. The multiplying DAC of  claim 1 , wherein the operational amplifier is a differential operational amplifier and the output of the operational amplifier comprises first and second outputs;
 wherein the first feedback switch is connected between the first output of the operational amplifier and the first sample capacitor; 
 wherein the input voltage is a differential voltage across first and second input lines, the first sampling capacitor circuit receiving the input voltage at the first input line; 
 and further comprising:
 a second sampling capacitor circuit, comprising a second sample capacitor, for receiving an input voltage at the second input line and storing the input voltage at the second sample capacitor in the first clock phase, the second sampling capacitor circuit having an output coupled to the second input of the operational amplifier; 
 a second feedback switch, connected between the second output of the operational amplifier and the second sample capacitor, for connecting the second sample capacitor in a feedback loop in the second clock phase; and 
 a second reference capacitor circuit, comprising:
 a second reference capacitor, coupled to the second input of the operational amplifier; 
 a second parallel capacitor, coupled to the second input of the operational amplifier; and 
 clocked switches, for coupling the input voltage at the second input line to the second reference capacitor and the second parallel capacitor in the first clock phase; 
 
 
 and wherein the switch circuitry is also for receiving a reference voltage that exceeds the second output level voltage by a factor, and for charging the second reference capacitor with the reference voltage in the second clock phase, the second reference capacitor having a capacitance less than a capacitance of the second sample capacitor by the factor. 
 
   
   
     3. The multiplying DAC of  claim 2 , wherein the first and second reference voltages exceed the first and second output level voltages, respectively, relative to a midpoint voltage between the first and second reference voltages. 
   
   
     4. The multiplying DAC of  claim 1 , further comprising:
 a shorting switch for shorting the parallel capacitor in the second clock phase. 
 
   
   
     5. The multiplying DAC of  claim 2 , further comprising:
 a shorting switch, for connecting the first and second parallel capacitors to one another in the second clock phase. 
 
   
   
     6. The multiplying DAC of  claim 1 , wherein the factor is two. 
   
   
     7. The multiplying DAC of  claim 6 , wherein the first reference capacitor and first parallel capacitor have the same capacitance as one another. 
   
   
     8. A multiplying digital-to-analog converter (DAC), comprising:
 an operational amplifier, having an input, and having an output for presenting an output analog signal over a range between a first voltage and a second voltage responsive to a signal at its input; 
 a first sample capacitor, having a first plate, and having a second plate connected to the input of the operational amplifier; 
 a first reference capacitor, having a first plate, and having a second plate connected to the input of the operational amplifier; 
 a first parallel capacitor, having a first plate, and having a second plate connected to the input of the operational amplifier; 
 a first sample switch, connected between an input and the first plate of the first sample capacitor, and clocked by a first clock phase; 
 a second sample switch, connected between the input and the first plate of the first reference capacitor, and clocked by the first clock phase; 
 a third sample switch, connected between the input and the first plate of the first parallel capacitor, and clocked by the first clock phase; 
 a first feedback switch, connected between the output of the operational amplifier and the first plate of the first sample capacitor, and clocked by a second clock phase; 
 reference voltage switch circuitry, connected between a reference voltage and the first plate of the first reference capacitor, and clocked by the second clock phase; and 
 a first shorting switch, connected to the first plate of the first parallel capacitor, and clocked by the second clock phase; 
 wherein the reference voltage exceeds the first voltage by a factor; and 
 wherein the first reference capacitor has a capacitance that is less than a capacitance of the first sample capacitor by the factor. 
 
   
   
     9. The multiplying DAC of  claim 8 , wherein the first shorting switch is for connecting the first plate of the first parallel capacitor to a ground voltage in the second clock phase. 
   
   
     10. The multiplying DAC of  claim 8 , wherein the reference voltage switch circuitry is for connecting the first plate of the first reference capacitor to a first reference voltage or to a second reference voltage, as the reference voltage, responsive to a digital value;
 wherein the first reference voltage exceeds the first voltage by the factor; 
 and wherein the second reference voltage exceeds the second voltage by the factor. 
 
   
   
     11. The multiplying DAC of  claim 8 , wherein the operational amplifier is a differential operational amplifier, the input of the operational amplifier comprising first and second inputs, and the output of the operational amplifier comprises first and second outputs;
 wherein the first feedback switch is connected between the first output of the operational amplifier and the first sample capacitor; 
 wherein the input voltage is a differential voltage across first and second input lines, the first and second sample switches receiving the input voltage at the first input line; 
 and further comprising:
 a second sample capacitor, having a first plate, and having a second plate connected to the second input of the operational amplifier; 
 a second reference capacitor, having a first plate, and having a second plate connected to the second input of the operational amplifier; 
 a second parallel capacitor, having a first plate, and having a second plate connected to the second input of the operational amplifier; 
 a fourth sample switch, connected between an input and the first plate of the second sample capacitor, and clocked by the first clock phase; 
 a fifth sample switch, connected between the input and the first plate of the second reference capacitor, and clocked by the first clock phase; 
 a sixth sample switch, connected between the input and the first plate of the second parallel capacitor, and clocked by the first phase; and 
 a second feedback switch, connected between the output of the operational amplifier and the first plate of the second sample capacitor, and clocked by the second clock phase; 
 
 wherein the reference voltage switch circuitry is also connected to the first plate of the second reference capacitor, and to first and second reference voltages; 
 and wherein the second reference capacitor has a capacitance that is less than a capacitance of the second sample capacitor by the factor. 
 
   
   
     12. The multiplying DAC of  claim 11 , wherein the reference voltage switch circuitry is for applying a selected differential reference voltage across the first plate of the first reference capacitor and the first plate of the second reference capacitor, responsive to a digital value;
 wherein the differential reference voltage is selected from a set of differential reference voltages comprising first and second polarities of a difference between a first reference voltage and a second reference voltage; 
 wherein the first reference voltage exceeds the first voltage by the factor; 
 and wherein the second reference voltage exceeds the second voltage by the factor. 
 
   
   
     13. The multiplying DAC of  claim 12 , wherein the factor is two. 
   
   
     14. The multiplying DAC of  claim 8 , wherein the factor is two. 
   
   
     15. A pipelined analog-to-digital converter, comprising:
 a plurality of pipeline stages connected in series, a first one of the pipeline stages connected to an analog input, each of the pipeline stages having a digital output, and having a residue output coupled in sequence to a next pipeline stage in the series; 
 a digital correction circuit, coupled to the digital output of each of the plurality of pipeline stages, for generating digital data corresponding to the analog input; and 
 a reference voltage generator, for generating a reference voltage; 
 wherein each of the plurality of pipeline stages comprises:
 a sample-and hold circuit, connected to the input of the pipeline stage; 
 an analog-to-digital converter, for digitizing a voltage at the output of the sample-and-hold circuit and presenting a digital value at the digital output of the pipeline stage; and 
 a multiplying digital-to-analog converter (DAC), comprising:
 an operational amplifier, having first and second inputs, and having an output for presenting the residue signal of the pipeline stage over an output range between first and second output level voltages responsive to signals received at the first and second inputs; 
 a first sampling capacitor circuit, comprising a first sample capacitor, for receiving an input voltage corresponding to the output of the sample-and-hold circuit and storing the input voltage at the first sample capacitor in a first clock phase, the first sampling capacitor circuit having an output coupled to a first input of the operational amplifier; 
 a first feedback switch, connected between the output of the operational amplifier and the first sample capacitor, for connecting the first sample capacitor in a feedback loop in a second clock phase; and 
 a first reference capacitor circuit, comprising:
 a first reference capacitor, coupled to the first input of the operational amplifier; 
 a first parallel capacitor, coupled to the first input of the operational amplifier; 
 clocked switches, for coupling the input voltage to the first reference capacitor and the first parallel capacitor in the first clock phase; and 
 
 switch circuitry, for charging the first reference capacitor with the reference voltage in the second clock phase; 
 
 
 wherein the reference voltage exceeds the first output level voltage by a factor; 
 and wherein the first reference capacitor having a capacitance less than a capacitance of the first sample capacitor by the factor. 
 
   
   
     16. The pipelined ADC of  claim 15 , wherein the first reference capacitor has a first plate, and has a second plate connected to the first input of the operational amplifier;
 and wherein the switch circuitry comprises:
 a first reference switch, connected between the reference voltage and the first plate of the first reference capacitor, for connecting the first plate of the first reference capacitor to the reference voltage in the second clock phase. 
 
 
   
   
     17. The pipelined ADC of  claim 16 , wherein switch circuitry is for connecting the first plate of the first reference capacitor to a first reference voltage or a second voltage, responsive to the digital value from the analog-to-digital converter in the pipeline stage;
 wherein the first and second reference voltages are generated by the reference voltage generator so that the first reference voltage exceeds the first output level voltage by the factor, and so that the second reference voltage exceeds the second output level voltage by the factor. 
 
   
   
     18. The pipelined ADC of  claim 17 , wherein the first and second reference voltages exceed the first and second output level voltages, respectively, relative to a midpoint voltage between the first and second reference voltages. 
   
   
     19. The pipelined ADC of  claim 18 , wherein the factor is two. 
   
   
     20. The pipelined ADC of  claim 15 , wherein the operational amplifier is a differential operational amplifier and the output of the operational amplifier comprises first and second outputs;
 wherein the first feedback switch is connected between the first output of the operational amplifier and the first sample capacitor; 
 wherein the input voltage is a differential voltage across first and second input lines, the first sampling capacitor circuit receiving the input voltage at the first input line; 
 and further comprising:
 a second sampling capacitor circuit, comprising a second sample capacitor, for receiving an input voltage at the second input line and storing the input voltage at the second sample capacitor in the first clock phase, the second sampling capacitor circuit having an output coupled to the second input of the operational amplifier; 
 a second feedback switch, connected between the second output of the operational amplifier and the second sample capacitor, for connecting the second sample capacitor in a feedback loop in the second clock phase; and 
 a second reference capacitor circuit, comprising:
 a second reference capacitor, coupled to the second input of the operational amplifier; 
 a second parallel capacitor, coupled to the second input of the operational amplifier; and 
 clocked switches, for coupling the input voltage at the second input line to the second reference capacitor and the second parallel capacitor in the first clock phase; 
 and wherein the switch circuitry is also for receiving a reference voltage that exceeds the second output level voltage by a factor, and for charging the second reference capacitor with the reference voltage in the second clock phase, the second reference capacitor having a capacitance less than a capacitance of the second sample capacitor by the factor.