Semiconductor memory device and defect remedying method thereof

Abstract

A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.

1. A semiconductor memory device formed on a semiconductor chip comprising:
 a plurality of first memory arrays; 
 a plurality of second memory arrays; 
 a first voltage generator; 
 a plurality of first bonding pads; 
 wherein the semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region, 
 wherein the third rectangle region is arranged between the first rectangle region and the second rectangle region, 
 wherein the plurality of first memory arrays are formed in the first rectangle region, 
 wherein the plurality of second memory arrays are formed in the second rectangle region, 
 wherein the voltage generator and the plurality of first bonding pads are arranged in the third rectangle region, 
 wherein the plurality of first bonding pads are arranged between the first rectangle region and the voltage generator, 
 wherein no bonding pads are arranged between the voltage generator and the plurality of second memory arrays. 
 
     
     
       2. A semiconductor memory device according to  claim 1 ,
 wherein the first voltage generator is a substrate voltage generator. 
 
     
     
       3. A semiconductor memory device according to  claim 2 , further comprising:
 a second voltage generator generating an internal voltage which is supplied to the first and second memory array; and 
 a plurality of second bonding pads, 
 wherein the plurality of second bonding pads are arranged between the second voltage generator and the first rectangle region, and 
 wherein no bonding pads are arranged between the second voltage generator and the second rectangle region. 
 
     
     
       4. A semiconductor memory device according to  claim 1 , further comprising:
 a second voltage generator generating an internal voltage which is supplied to the first and second memory array; and 
 a plurality of second bonding pads, 
 wherein the plurality of second bonding pads are arranged between the second voltage generator and the first rectangle region, and 
 wherein no bonding pads are arranged between the second voltage generator and the second rectangle region. 
 
     
     
       5. A semiconductor memory device according to  claim 1 , wherein the semiconductor device is DRAM. 
     
     
       6. A semiconductor memory device according to  claim 2 , wherein the semiconductor device is DRAM. 
     
     
       7. A semiconductor memory device according to  claim 3 , wherein the semiconductor device is DRAM. 
     
     
       8. A semiconductor memory device according to  claim 4 , wherein the semiconductor device is DRAM. 
     
     
       9. A semiconductor memory device according to  claim 1 ,
 wherein the first rectangle region, the third rectangle region, and the second rectangle region are sequentially arranged in a first direction, 
 wherein the plurality of first bonding pads are arranged in a second direction which is across the first direction. 
 
     
     
       10. A semiconductor memory device according to  claim 9 ,
 wherein the plurality of first bonding pads are arranged in two rows in the second direction.