Low-voltage triggered PNP for ESD protection in mixed voltage I/O interface

Abstract

An low-voltage triggered PNP device for input signals with voltage level larger than VDD or less than VSS. The ESD protection device provides an ESD path from a first to a second node for protection of an internal circuit. The device comprises a substrate of a first conductivity type coupled to the first node, a first doped region of a second conductivity type in the substrate, wherein the first doped region is floated, a second doped region of the first conductivity type in the first doped region coupled to the second node, and a third doped region in the substrate, adjacent to the first doped region, to have a low trigger voltage.

1. An ESD protection device for input signals with voltage level larger than VDD or less than VSS, which provides an ESD path from a first to a second node, the device comprising:
 a substrate of a first conductivity type coupled to the first node; 
 a first doped region of a second conductivity type in the substrate, wherein the first doped region is floated; 
 a second doped region of the first conductivity type in the first doped region, coupled to the second node; and 
 a third doped region in the substrate, adjacent to the first doped region. 
 
   
   
     2. The ESD protection device as claimed in  claim 1 , wherein the third doped region is of the second conductivity type and the doping concentration of the third doped region is higher than that of the first doped region. 
   
   
     3. The ESD protection device as claimed in  claim 2  further comprising a fourth doped region of the first conductivity type in the substrate, coupling the substrate to the first node. 
   
   
     4. The ESD protection device as claimed in  claim 3  further comprising:
 an ESD implantation region in the substrate and immediately below the third doped region; and 
 a plurality of isolation layers in the substrate, isolating the second, third and fourth doped regions from each other. 
 
   
   
     5. The ESD protection device as claimed in  claim 4 , wherein the first and second conductivity types are P and N respectively. 
   
   
     6. The ESD protection device as claimed in  claim 2 , wherein the internal circuit receives a first power supply voltage and a second power supply voltage lower than the first power supply voltage through a first and second power line respectively, and an input signal through an I/O pad, the first and second node coupled to the second power line and the I/O pad respectively, wherein the input signal has a maximum voltage level higher than the first power supply voltage and a minimum voltage level lower than the second power supply voltage. 
   
   
     7. The ESD protection device as claimed in  claim 4  further comprising:
 an ESD clamp circuit coupled between the first and second power line; and 
 a diode having an anode coupled to the first node and a cathode coupled to the second power line. 
 
   
   
     8. The ESD protection device as claimed in  claim 4  further comprising:
 an ESD clamp circuit coupled between the first and second power line; and 
 a plurality of diodes serially connected in a same direction between the first node and the second power line. 
 
   
   
     9. The ESD protection device as claimed in  claim 1 , wherein the third doped region is of the first conductivity type and the doping concentration of the third doped region is higher than that of the substrate. 
   
   
     10. The ESD protection device as claimed in  claim 9  further comprising a fourth doped region of the first conductivity in the substrate, coupling the substrate to the first node. 
   
   
     11. The ESD protection device as claimed in  claim 10  further comprising:
 an ESD implantation region in the substrate and immediately below the third doped region; and 
 a plurality of isolation layers in the substrate, isolating the second, third and fourth doped regions from each other. 
 
   
   
     12. The ESD protection device as claimed in  claim 11 , wherein the first and second conductivity types are P and N respectively. 
   
   
     13. The ESD protection device as claimed in  claim 9 , wherein the internal circuit receives a first power supply voltage and a second power supply voltage lower than the first power supply voltage through a first and second power line respectively, and receives an input signal through an I/O pad, the first and second node are coupled to the second power line and the I/O pad respectively, and the input signal has a maximum voltage level higher than the first power supply voltage and a minimum voltage level lower than the second power supply voltage. 
   
   
     14. The ESD protection device as claimed in  claim 13  further comprising:
 an ESD clamp circuit coupled between the first and second power line; and 
 a diode having an anode coupled to the first node and a cathode coupled to the second power line. 
 
   
   
     15. The ESD protection device as claimed in  claim 13  further comprising:
 an ESD clamp circuit coupled between the first and second power line; and 
 a plurality of diodes serially connected in a same direction between the first node and the second power line. 
 
   
   
     16. The ESD protection device as claimed in  claim 1 , wherein the third doped region is of the first conductivity type and couples the substrate to the first node and the doping concentration of the third doped region is higher than that of the substrate. 
   
   
     17. The ESD protection device as claimed in  claim 16  further comprising:
 an ESD implantation region in the substrate and immediately below the third doped region; and 
 a plurality of isolation layers in the substrate, isolating the second and third doped region from each other. 
 
   
   
     18. The ESD protection device as claimed in  claim 17 , wherein the first and second conductivity types are P and N respectively. 
   
   
     19. The ESD protection device as claimed in  claim 16 , wherein the internal circuit receives a first power supply voltage and a second power supply voltage lower than the first power supply voltage through a first and second power line respectively, and receives an input signal through an I/O pad, the first and second node are coupled to the second power line and the I/O pad respectively, and the input signal has a maximum voltage level higher than the first power supply voltage and a minimum voltage level lower than the second power supply voltage. 
   
   
     20. The ESD protection device as claimed in  claim 19  further comprising:
 an ESD clamp circuit coupled between the first and second power lines; and 
 a diode having an anode coupled to the first node and a cathode coupled to the second power line. 
 
   
   
     21. The ESD protection device as claimed in  claim 19  further comprising:
 an ESD clamp circuit coupled between the first and second power lines; and 
 a plurality of diodes serially connected in a same direction between the first node and the second power line. 
 
   
   
     22. An ESD protection device for input signals with voltage level larger than VDD or less than VSS, which provides an ESD path from a first to a second node and the second to a third node, the device comprising:
 a substrate of a first conductivity type coupled to the first node; 
 a first doped region of a second conductivity type in the substrate, wherein the first doped region is floated; 
 a second doped region of the first conductivity type in the first doped region, coupled to the second node; 
 a third doped region in the substrate, adjacent to the first doped region; and 
 a fourth doped region of the first conductivity type in the first doped region, coupled to the third node. 
 
   
   
     23. The ESD protection device as claimed in  claim 22 , wherein the third doped region is of the second conductivity type and the doping concentration of the third doped region is higher than that of the first doped region. 
   
   
     24. The ESD protection device as claimed in  claim 23  further comprising a fifth doped region of the first conductivity type in the substrate, coupling the substrate to the first node. 
   
   
     25. The ESD protection device as claimed in  claim 24  further comprising:
 an ESD implantation region in the substrate and immediately below the third doped region; and 
 a plurality of isolation layers in the substrate, isolating the second, third, fourth and fifth doped regions from each other. 
 
   
   
     26. The ESD protection device as claimed in  claim 25 , wherein the first and second conductivity types are P and N respectively. 
   
   
     27. The ESD protection device as claimed in  claim 23 , wherein the internal circuit receives a first power supply voltage and a second power supply voltage lower than the first power supply voltage through a first and second power line respectively, and receives an input signal through an I/O pad, the first and second node are coupled to the second power line and the I/O pad respectively, and the input signal has a maximum voltage level higher than the first power supply voltage and a minimum voltage level lower than the second power supply voltage. 
   
   
     28. The ESD protection device as claimed in  claim 22 , wherein the third doped region is of the first conductivity type and the doping concentration of the third doped region is higher than that of the substrate. 
   
   
     29. The ESD protection device as claimed in  claim 28  further comprising a fifth doped region of the first conductivity in the substrate, coupling the substrate to the first node. 
   
   
     30. The ESD protection device as claimed in  claim 29  further comprising:
 an ESD implantation region in the substrate and immediately below the third doped region; 
 a plurality of isolation layers in the substrate, isolating the second, third, fourth and fifth doped regions from each other. 
 
   
   
     31. The ESD protection device as claimed in  claim 30 , wherein the first and second conductivity types are P and N respectively. 
   
   
     32. The ESD protection device as claimed in  claim 28 , wherein the internal circuit receives a first power supply voltage and a second power supply voltage lower than the first power supply voltage through a first and second power line respectively, and receives an input signal through an I/O pad, the first and second node are coupled to the second power line and the I/O pad respectively, and the input signal has a maximum voltage level higher than the first power supply voltage and a minimum voltage level lower than the second power supply voltage. 
   
   
     33. The ESD protection device as claimed in  claim 22 , wherein the third doped region is of the first conductivity type and couples the substrate to the first node and the doping concentration of the third doped region is higher than that of the substrate. 
   
   
     34. The ESD protection device as claimed in  claim 33  further comprising:
 an ESD implantation region in the substrate and immediately below the third doped region; and 
 a plurality of isolation layers in the substrate, isolating the second, third and fourth doped regions from each other. 
 
   
   
     35. The ESD protection device as claimed in  claim 34 , wherein the first and second conductivity types are P and N respectively. 
   
   
     36. The ESD protection device as claimed in  claim 33 , wherein the internal circuit receives a first power supply voltage and a second power supply voltage lower than the first power supply voltage through a first and second power line respectively, and receives an input signal through an I/O pad, the first and second node are coupled to the second power line and the I/O pad respectively, and the input signal has a maximum voltage level higher than the first power supply voltage and a minimum voltage level lower than the second power supply voltage.