Laser-induced critical parameter analysis of CMOS devices

Abstract

A technique is described for performing critical parameter analysis (CPA) of a semiconductor device (DUT) by combining the capabilities of conventional automated test equipment (ATE) with a focused optical beam scanning device such as a laser scanning microscope (LSM). The DUT is provided with a fixture such that it can be simultaneously scanned by the LSM or a similar device and exercised by the ATE. The ATE is used to determine pass/fail boundaries of operation of the DUT. Repeatable pass/fail limits (for timing, levels, etc.) are determined utilizing standard test patterns and methodologies. The ATE vector pattern(s) can then be programmed to “loop” the test under a known passing or failing state. When light energy from the LSM scanning beam sufficiently disturbs the DUT to produce a transition (i.e., to push the device outside of its critical parameter limits), this transition is indicated on the displayed image of the DUT, indicating to the user which elements of the DUT were implicated in the transition.

1. A system for critical parameter analysis (CPA) of a semiconductor device (DUT), comprising:
 a laser scanning microscope (LSM); 
 automated test apparatus (ATE) for providing predefined stimulus to the semiconductor device (DUT), for comparing responses from the semiconductor device (DUT) against a set of predefined expected responses, and for generating a short output pulse when a difference is detected between responses from said semiconductor device (DUT) and said predefined expected responses, said automated test apparatus being connected to the DUT while the DUT is disposed within a scanning chamber of said laser scanning microscope (LSM); 
 display means for displaying an image of said semiconductor device produced by said laser scanning microscope (LSM); 
 means for overlaying a visible representation of said short output pulse on said displayed image to indicate a corresponding position on the semiconductor device (DUT) of a scanning beam of the laser scanning microscope (LSM) at the time the output pulse was generated; and 
 means for simultaneously scanning said semiconductor device (DUT) with said laser scanning microscope (LSM) while said ATE repeatedly applies said predefined stimulus to said DUT and compares responses therefrom against said predefined expected responses; 
 wherein
 the automated test apparatus (ATE) and the semiconductor device (DUT) form a closed loop feedback system; 
 the automated test apparatus (ATE) is programmed to ‘break’ in or out of a vector loop which is detecting pass/fail operation of the semiconductor device (DUT); and 
 said automated test apparatus (ATE) is configured to repeatedly cycle (“short-cycle”) said predefined stimulus from a starting point up to a point of failure when such failure is detected. 
 
 
   
   
     2. A system according to  claim 1 , wherein said semiconductor device (DUT) is fixtured such that ATE connections to the device are made within a scanning chamber of the laser scanning microscope (LSM). 
   
   
     3. A system according to  claim 1 , further comprising:
 image converting means for representing output from the laser scanning microscope (LSM) as a viewable video signal and for overlaying the output signal indication from the automated test apparatus (ATE) on said viewable video signal; and 
 display means for viewing said video signal with overlaid automated test apparatus (ATE) output signal indication. 
 
   
   
     4. A system according to  claim 3 , wherein said overlaid ATE output signal indication produces a visible spot on said display means at a location on a simultaneously displayed image of the semiconductor device (DUT) that indicates the location on the semiconductor device (DUT) that was illuminated by the laser scanning microscope (LSM) at the time the automated test apparatus (ATE) output signal indication was produced. 
   
   
     5. A system according to  claim 1 , wherein said predefined stimulus is provided to said automated test apparatus (ATE) in the form of a set of test vectors. 
   
   
     6. A system according to  claim 1 , wherein said predefined expected responses are provided to said automated test apparatus (ATE) in the form of a set of test vectors. 
   
   
     7. A system according to  claim 1 , wherein said automated test apparatus (ATE) is configured to repeatedly apply said predefined stimulus to said semiconductor device (DUT) in a test “loop.” 
   
   
     8. A system according to  claim 1 , wherein said output pulse is a short pulse generated when a difference is detected between responses by said semiconductor device (DUT) to said predefined stimulus and the predefined expected responses. 
   
   
     9. A method for critical parameter analysis (CPA) of a semiconductor device (DUT), comprising:
 providing a focused optical beam scanning device; 
 providing automated test apparatus (ATE) for providing predefined stimulus to the semiconductor device (DUT), for comparing responses from the semiconductor device (DUT) against a set of predefined expected responses, and for generating a short output pulse when a difference is detected between responses from said semiconductor device (DUT) and said predefined expected responses, said automated test apparatus being connected to the DUT while the DUT is disposed within a scanning chamber of said laser scanning microscope (LSM); 
 displaying an image of said semiconductor device produced by said laser scanning microscope (LSM); 
 overlaying a visible representation of said short output pulse on said displayed image to indicate a corresponding position on the semiconductor device (DUT) of a scanning beam of the laser scanning microscope (LSM) at the time the output pulse was generated; and 
 simultaneously scanning said semiconductor device (DUT) with said laser scanning microscope (LSM) while repeatedly applying said redefined stimulus to said DUT and comparing responses therefrom against said predefined expected responses using said ATE; 
 wherein
 the automated test apparatus (ATE) and the semiconductor device (DUT) form a closed loop feedback system; 
 the automated test apparatus (ATE) is programmed to ‘break’ in or out of a vector loop which is detecting pass/fail operation of the semiconductor device (DU); and 
 said automated test apparatus (ATE) is configured to repeatedly cycle (“short-cycle”) said predefined stimulus from a starting point up to a point of failure when such failure is detected. 
 
 
   
   
     10. A method according to  claim 9 , wherein said focused optical beam scanning device is a laser scanning microscope (LSM). 
   
   
     11. A method according to  claim 9 , wherein the automated test apparatus (ATE) is synchronized with the focused optical beam scanning device. 
   
   
     12. A method according to  claim 9 , further comprising providing optical signatures that only appear on the gate level devices responsible for the failing test. 
   
   
     13. A method according to  claim 9 , further comprising providing real time feedback to the focused optical beam scanning device and subsequent optical images acquired. 
   
   
     14. A method according to  claim 9 , further comprising:
 fixturing said semiconductor device (DUT) such that ATE connections to the device are made within a scanning chamber of the focused optical beam scanning device. 
 
   
   
     15. A method according to  claim 9 , further comprising:
 representing an output from the focused optical beam scanning device as a viewable video signal and for overlaying the output signal indication from the automated test apparatus (ATE) on said viewable video signal; and 
 viewing said video signal with overlaid automated test apparatus (ATE) output signal indication. 
 
   
   
     16. A method according to  claim 15 , wherein said overlaid ATE output signal indication produces a visible spot on said display means at a location on a simultaneously displayed image of the semiconductor device (DUT) that indicates the location on the semiconductor device (DUT) that was illuminated by the focused optical beam scanning device at the time the automated test apparatus (ATE) output signal indication was produced. 
   
   
     17. A method according to  claim 9 , wherein said predefined stimulus is provided to said automated test apparatus (ATE) in the form of a set of test vectors. 
   
   
     18. A method according to  claim 9 , wherein said predefined expected responses are provided to said automated test apparatus (ATE) in the form of a set of test vectors. 
   
   
     19. A method according to  claim 9 , wherein said automated test apparatus (ATE) is configured to repeatedly apply said predefined stimulus to said semiconductor device (DUT) in a test “loop.” 
   
   
     20. A method according to  claim 9 , wherein said output pulse is a short pulse generated when a difference is detected between responses by said semiconductor device (DUT) to said predefined stimulus and the predefined expected responses.