Differential stage voltage offset trim circuitry

Abstract

Differential stage voltage offset trim circuitry involves the use of one or more trim circuits, each of which is dedicated to trimming one particular source of voltage offset (V os ) error for a “main” differential pair. One trim circuit may be dedicated to trimming V os error that arises due to mismatch between the main pairs' threshold voltages, and another trim circuit may be dedicated to trimming V os error that arises due to mismatch between the main pairs' beta values. Another trim circuit can trim V os error due to gamma mismatch between the main pair transistors, and respective trim circuits can be employed to trim V os error that arises due to threshold mismatch and/or beta mismatch between the transistors of an active load driven by the main pair. Several trim circuits may be employed simultaneously to reduce offset errors that arise from each of several sources.

1. A differential stage, comprising:
 a main differential transistor pair which is biased to conduct respective output currents in response to a differential input voltage; 
 a second differential transistor pair; 
 circuitry connected to said second differential transistor pair and arranged to make said second pair's common-mode input voltage approximately equal to said main pair's common-mode input voltage; and 
 first and second programmable current sources arranged to create a desired differential voltage across said second differential transistor pair such that the transistors of said second pair conduct respective trim currents, said trim currents coupled to respective ones of said output currents, said first and second programmable current sources programmed such that said trim currents reduce voltage offset error in said main differential pair which arises due to the transistors of said main pair having mismatched threshold voltages. 
 
   
   
     2. A differential stage, comprising:
 a main differential pair comprising first and second transistors, each of which has a control input and first and second current terminals, said second current terminals connected together at a first node; 
 a first bias current source connected to said first node which provides a first bias current to said main differential pair such that said first and second transistors conduct respective output currents at their first current terminals in response to a differential input voltage applied across their control inputs, said first differential pair having an associated common-mode input voltage; 
 a second differential pair comprising third and fourth transistors, each of which has a control input and first and second current terminals, said second current terminals connected together at a second node; 
 a second bias current source connected to provide a second bias current to said second differential pair; 
 circuitry connected to said second differential pair and arranged to make said second differential pair's common-mode input voltage approximately equal to said main pair's common-mode input voltage; and 
 first and second trim current sources arranged to provide respective currents I 1  and I 2  to the control inputs of said third and fourth transistors, respectively, to create a desired differential voltage across said second differential pair such that said third and fourth transistors conduct respective trim currents I trim1  and I trim2 , said trim currents coupled to respective ones of said output currents. 
 
   
   
     3. The input stage of  claim 2 , wherein the ratio between the first and second bias currents is approximately equal to the ratio between the sizes of said first and second transistors with respect to the sizes of said third and fourth transistors, respectively. 
   
   
     4. The input stage of  claim 2 , wherein said circuitry comprises:
 first and second resistors connected in series between the control inputs of said third and fourth transistors, the junction of said first and second resistors being a third node; and 
 a servomechanism having its inputs connected to said first and second nodes and its output connected to said third node such that the voltage at said second node is servoed to be approximately equal to the voltage at said first node. 
 
   
   
     5. The input stage of  claim 4 , wherein said first and second resistors each have a resistance R, and said currents I 1 =I 2 =I t , such that the differential trim current I trim1 −I trim2  is approximately given by:
     I   trim1   −I   trim2 =2 *I   t   *R*gm   2 , 
 
     where gm 2  is the transconductance of the second differential pair, and said second differential pair produces an input-referred offset voltage V off  for said main pair given by:
     V   off =2 *I   t   *R*gm   2   /gm   1   
 
     where gm 1  is the transconductance of the main differential pair. 
   
   
     6. The input stage of  claim 5 , wherein said resistors and said trim current sources are arranged such that I t *R is approximately constant over temperature. 
   
   
     7. The input stage of  claim 5 , wherein said resistors and said trim current sources are arranged such that I t *R has a desired temperature characteristic. 
   
   
     8. The input stage of  claim 6 , wherein said trim current sources comprise:
 at least one bandgap voltage source which produces a bandgap voltage; and 
 respective resistors, said bandgap voltage connected across respective ones of said resistors to produce said currents I 1  and I 2 . 
 
   
   
     9. The input stage of  claim 2 , wherein said main and second differential pairs are MOSFETs. 
   
   
     10. The input stage of  claim 9 , wherein said first and second trim current sources are programmable current sources, said first and second trim current sources programmed to produce trim currents I 1  and I 2  to substantially reduce voltage offset error in said main differential pair which arises due to said first and second transistors having mismatched threshold voltages. 
   
   
     11. The input stage of  claim 2 , wherein said main and second differential pairs are bipolar transistors. 
   
   
     12. The input stage of  claim 2 , wherein said circuitry comprises:
 a dummy differential pair comprising fifth and sixth transistors, each of which has a control input and first and second current terminals, said control inputs connected to receive said differential input voltage and said second current terminals connected together at a third node; 
 a third bias current source connected to said third node which provides a third bias current to said third differential pair such that said fifth and sixth transistors conduct respective currents at their first current terminals in response to said differential input voltage; and 
 a diode circuit connected at one terminal to said third node and at its other terminal to the control inputs of said second differential pair via respective resistors, such that the voltage at said second node is servoed to be approximately equal to the voltage at said first node. 
 
   
   
     13. The input stage of  claim 12 , wherein the ratio between the first and third bias currents is approximately equal to the ratio between the sizes of said first and second transistors with respect to the sizes of said fifth and sixth transistors. 
   
   
     14. The input stage of  claim 13 , wherein said diode circuit comprises:
 a diode-connected transistor; and 
 a current source connected to provide a bias current to said diode-connected transistor such that the current density through said diode-connected transistor is approximately equal to the current densities through said main pair, said second pair, and said dummy pair. 
 
   
   
     15. The input stage of  claim 2 , wherein said first trim current source is connected between the control input of said third transistor and a circuit common point and said second trim current source is connected between the control input of said fourth transistor and said circuit common point. 
   
   
     16. The input stage of  claim 2 , further comprising third and fourth current sources connected to the first terminals of said first and second transistors, respectively, and arranged to provide the common mode components of said output currents. 
   
   
     17. The input stage of  claim 2 , wherein said circuitry comprises:
 a dummy differential pair comprising fifth and sixth transistors, each of which has a control input and first and second current terminals, said control inputs connected to receive said differential input voltage, said second current terminals connected together at a third node, and said first current terminals connected together at a fourth node; 
 a third bias current source connected to said third node which provides a third bias current to said third differential pair such that said fifth and sixth transistors conduct respective currents at their first current terminals in response to said differential input voltage; 
 seventh and eighth transistors, each of which has a control input and first and second current terminals, said first and second current terminals connected between a supply voltage and fifth and sixth nodes, respectively; 
 ninth and tenth transistors, each of which has a control input and first and second current terminals, said first and second current terminals connected between said fifth and sixth nodes and seventh and eighth nodes, respectively; 
 an eleventh transistor having a control input and first and second current terminals, said eleventh transistor diode-connected between said seventh node and a circuit common point; 
 a twelfth transistor having a control input and first and second current terminals, said first and second current terminals connected between said eighth node and said circuit common point; 
 the control inputs of said seventh and eighth transistors connected to a first bias voltage; 
 the control inputs of said ninth and tenth transistors connected to a second bias voltage; 
 the control inputs of said eleventh and twelfth transistors connected together; and 
 a thirteenth transistor having a control input and first and second current terminals, said first and second current terminals connected between said sixth node and said third node and said control input connected to said eighth node; 
 said eighth node connected to the control inputs of said second differential pair via respective resistors, such that the voltage at said second node is servoed to be approximately equal to the voltage at said first node. 
 
   
   
     18. A differential input stage, comprising:
 a main differential pair comprising first and second transistors and biased with a first bias current such that said main pair conducts respective output currents in response to a differential input voltage; 
 at least one voltage offset trim circuit, said at least one voltage offset trim circuit comprising:
 a trim circuit adjusted to reduce voltage offset error in said main differential pair that arises due to mismatch between the threshold voltages of said first and second transistors, comprising in addition to said main differential pair:
 a second differential transistor pair; 
 circuitry connected to said second differential transistor pair and arranged to make said second pair's common-mode input voltage approximately equal to said main pair's common-mode input voltage; and 
 first and second programmable current sources connected to create a desired differential voltage across said second differential transistor pair such that the transistors of said second pair conduct respective trim currents, said trim currents coupled to respective ones of said output currents, said first and second programmable current sources programmed such that said trim currents substantially reduce voltage offset error in said main differential pair which arises due to the transistors of said main pair having mismatched threshold voltages; and/or 
 
 a trim circuit adjusted to reduce voltage offset error in said main differential pair that arises due to beta mismatch between said first and second transistors, comprising in addition to said main differential pair:
 a second differential transistor pair biased with a second bias current such that said second pair conducts respective output currents in response to said differential input voltage, wherein the ratio between said second and first bias currents is approximately 1:N and the ratio between the sizes of said main pair transistors with respect to the sizes of said second pair transistors, respectively, is approximately 1:N, such that said second pairs' output currents are proportional to said main pairs' average drain current; and 
 a digital-to-analog converter (DAC) connected to receive said second pairs' output currents at a reference current input and arranged to produce trim currents at respective current outputs, said trim currents varying with said second pairs' output currents and thus said main pairs' average drain current and scaled by a digital value applied to said DAC's digital input, said trim currents coupled to respective ones of said main pair's output currents, said DAC programmed to reduce voltage offset error in said main differential pair that arises due to beta mismatch between the transistors of said main pair; and/or 
 
 a trim circuit adjusted to reduce voltage offset error in said main differential pair that arises due to gamma mismatch between said first and second transistors, comprising in addition to said main differential pair:
 circuitry which receives said differential input voltage and is arranged to produce a reference current which varies linearly or linearly with an additive constant with the stage's source voltage relative to ground; 
 a digital-to-analog converter (DAC) connected to receive said reference current at a reference current input and arranged to produce currents I 1  and I 2  at respective current outputs, said currents varying with said reference current and scaled by a digital value applied to said DAC's digital input; and 
 a second differential transistor pair which receives currents I 1  and I 2  and is biased to conduct respective trim currents in response, said trim currents coupled to respective ones of said main pair's output currents, said DAC programmed to reduce voltage offset error in said main pair that arises due to gamma mismatch between the transistors of said main pair; and/or 
 
 a trim circuit adjusted to reduce voltage offset error in said main differential pair that arises due to threshold mismatch between the transistors of an active load driven by said main differential pair, comprising in addition to said main differential pair:
 an active load comprising third and fourth transistors connected in series between a supply voltage and said first and second transistors, respectively, said active load transistors biased with a bias voltage such that they conduct said output currents; 
 a second differential pair comprising fifth and sixth transistors and biased with said bias voltage; and 
 first and second programmable current sources arranged to provide respective currents I 1  and I 2  to said fifth and sixth transistors, respectively, to create a desired differential voltage across said second differential pair such that said fifth and sixth transistors conduct respective trim currents, said trim currents coupled to respective ones of said output currents, said first and second trim current sources programmed to produce trim currents I 1  and I 2  to match the currents conducted by said third and fourth transistors and to thereby reduce voltage offset error in said main differential pair which arises due to said active load transistors having mismatched threshold voltages; and/or 
 
 a trim circuit adjusted to reduce voltage offset error in said main differential pair that arises due to beta mismatch between the transistors of an active load driven by said main differential pair, comprising in addition to said main differential pair:
 an active load comprising third and fourth transistors connected in series between a supply voltage and said first and second transistors, respectively, said active load transistors biased with a bias voltage such that they conduct said output currents; 
 a fifth transistor connected to said supply voltage and said bias voltage such that said fifth transistor is biased like said active load transistors and conducts a reference current which varies with said bias voltage; and 
 a digital-to-analog converter (DAC) connected to receive said reference current at a reference current input and arranged to produce first and second trim currents at respective current outputs, said currents varying with said reference current and scaled by a digital value applied to said DAC's digital input; 
 said trim currents coupled to respective ones of said main pair's output currents, said DAC programmed to match the currents conducted by said third and fourth transistors and to thereby reduce voltage offset error in said main differential pair that arises due to beta mismatch between said third and fourth transistors. 
 
 
 
   
   
     19. The differential input stage of  claim 18 , wherein the second differential pair of said trim circuit adjusted to reduce voltage offset error in said main differential pair that arises due to gamma mismatch and the second differential pair of the trim circuit adjusted to reduce voltage offset error in said main differential pair that arises due to mismatch between the threshold voltages of said first and second transistors are the same pair. 
   
   
     20. A method of reducing voltage offset error that arises due to a mismatch between the threshold voltages of a main FET differential pair biased to conduct respective output currents in response to a differential input voltage, comprising:
 providing a second FET differential pair; 
 making said second pair's common-mode input voltage approximately equal to said main pair's common-mode input voltage; 
 providing first and second programmable currents to said second pair to create a desired differential voltage across said second pair such that the FETs of said second pair conduct respective trim currents; 
 coupling said trim currents to respective ones of said output currents; and 
 adjusting said first and second programmable currents such that said trim currents reduce voltage offset error in said main differential pair which arises due to the transistors of said main pair having mismatched threshold voltages.