1/N-rate encoder circuit topology

Abstract

An encoder circuit and a related method for its operation, in which digital encoding, such as differential phase-shift keyed (DPSK) encoding, is performed as a parallel operation on N bits at a time. Each encoded bit is both output in parallel with the others of the N bits and is coupled as an input to encode the immediately next bit in the input data stream. The N th encoded bit is fed back to the first encoder stage for use in encoding the (N+1) th bit in the input stream. The encoder typically includes a serial-to-parallel converter at the encoder inputs, and a parallel-to-serial converter at the encoder outputs.

1. A reduced-rate differential phase shift keyed (DPSK) encoder, comprising:
 a set of N encoder stages, wherein each stage comprises an exclusive-OR gate having a first input terminal for receiving, as an input, one of N parallel data bits, and a second input terminal, for receiving as an input, an output signal from an encoder stage responsible for encoding an immediately prior data bit; 
 wherein each encoder stage further includes a bit storage device into which the output of the exclusive-OR gate is coupled upon the occurrence of a clocking signal applied to the bit storage device; 
 and wherein output from the N th -stage bit storage device is fed back as an input to a first-stage exclusive-OR gate, to be used in the encoding of a (N+1) th , (2N+1) th  and subsequent data bits that are input to the first-stage exclusive-OR gate in second and subsequent cycles of parallel encoding operations. 
 
     
     
       2. A reduced-rate DPSK encoder as defined in  claim 1 , wherein N=2 and the encoder operates as a half-rate encoder. 
     
     
       3. A reduced-rate DPSK encoder as defined in  claim 1 , and further comprising a serial-to-parallel converter, for converting a serial data stream to N-bit blocks of input data for coupling to the N encoder stages. 
     
     
       4. A reduced-rate DPSK encoder as defined in  claim 3 , and further comprising a parallel-to-serial converter, for converting N-bit blocks of encoded output data into a serial encoded output data stream. 
     
     
       5. A method for encoding data in accordance with a differential phase shift keyed (DPSK) encoding scheme, but at a reduced encoding rate, the method comprising:
 inputting in parallel N data bits to a set of N respective encoder stages, wherein each stage comprises an exclusive-OR gate having a first input terminal for receiving one of the N parallel data bits, and a second input terminal; 
 coupling into the second input terminal of each stage an output signal from an encoder stage responsible for encoding an immediately prior data bit; 
 clocking the output of each encoder stage into a bit storage device included in the stage; and 
 coupling the output from the N th -stage bit storage device back as an input to a first-stage exclusive-OR gate, to be used in the encoding of a (N+1) th , (2N+1) th  and subsequent data bits that are input to the first-stage exclusive-OR gate in second and subsequent cycles of parallel encoding operations. 
 
     
     
       6. A method as defined in  claim 5 , wherein N=2 and the method performs a half-rate encoding process. 
     
     
       7. A method as defined in  claim 5 , and further comprising:
 converting a serial data input stream to N-bit blocks of parallel data, for input to N encoder stages. 
 
     
     
       8. A method as defined in  claim 7 , and further comprising:
 converting N-bit blocks of parallel output data from the N encoder stages to a serial data stream. 
 
     
     
       9. A reduced-rate digital encoder operating in accordance with an encoding scheme wherein the binary value of each successive encoded bit depends in part on the binary value of the immediately preceding encoded bit, the reduced-rate digital encoder comprising:
 a set of N encoder stages, wherein each stage comprises digital logic having a first input terminal for receiving, as an input, one of N parallel data bits, and a second input terminal, for receiving as an input, an output signal from an encoder stage responsible for encoding an immediately prior data bit; 
 wherein each encoder stage further includes a bit storage device into which the output of the digital logic is coupled upon the occurrence of a clocking signal applied to the bit storage device; 
 and wherein output from the Nth-stage bit storage device is fed back as an input to a first-stage digital logic, to be used in the encoding of a (N+1) th , (2N+1) th  and subsequent data bits that are input to the first-stage digital logic in second and subsequent cycles of parallel encoding operations. 
 
     
     
       10. A reduced-rate digital encoder as defined in  claim 9 , wherein N=2 and the encoder operates as a half-rate encoder. 
     
     
       11. A reduced-rate digital encoder as defined in  claim 9 , and further comprising a serial-to-parallel converter, for converting a serial data stream to N-bit blocks of input data for coupling to the N encoder stages. 
     
     
       12. A reduced-rate digital encoder as defined in  claim 11 , and further comprising a parallel-to-serial converter, for converting N-bit blocks of encoded output data into a serial encoded output data stream.