Method of manufacturing a nonvolatile semiconductor memory device

Abstract

In a method of manufacturing a semiconductor device having a nonvolatile semiconductor memory element with a two-layered gate structure in which a floating gate and control gate are stacked, a polysilicon layer serving as the floating gate is stacked on a silicon substrate via a tunnel insulating film. Then, the silicon layer, tunnel insulating film, and substrate are selectively etched to form an element isolation trench. A nitride film is formed on the sidewall surface of the silicon layer exposed into the element isolation trench. An oxide film is buried in the element isolation trench. A conductive film serving as the control gate is stacked on the oxide film and silicon layer via an electrode insulating film. The conductive film, electrode insulating film, and silicon layer are selectively etched to form the control gate and floating gate.

What is claimed is: 
     
       1. A method of manufacturing a semiconductor device having a nonvolatile semiconductor memory element with a two-layered gate structure, comprising the steps of:
 forming a tunnel insulating film and one of a polysilicon layer and an amorphous silicon layer serving as a floating gate electrode on one major surface of a semiconductor substrate; 
 selectively etching the one of the polysilicon layer and the amorphous silicon layer, the tunnel insulating film, and the semiconductor substrate using a mask having a pattern corresponding to an element isolation trench so as to form the element isolation trench; 
 forming a nitride film on a first sidewall surface, perpendicular to a channel width direction of the floating gate electrode, of the one of the polysilicon layer and the amorphous silicon layer exposed into the element isolation trench and burying an element isolation insulating film in the element isolation trench; 
 stacking an electrode insulating film and a conductive film serving as a control gate electrode on the element isolation insulating film and the one of the polysilicon layer and the amorphous silicon layer; 
 selectively etching the conductive film, the electrode insulating film, and the one of the polysilicon layer and the amorphous silicon layer using a mask having a pattern corresponding to the control gate electrode so as to form the control gate electrode and floating gate electrode; and 
 forming a silicon oxide film on a second sidewall surface perpendicular to a channel length direction of the floating gate electrode, in an atmosphere containing radical oxygen, so that a thickness in the channel length direction of the silicon oxide film is greater at a portion on an element isolation insulating film end of the second sidewall surface than at a center portion of the second sidewall surface. 
 
     
     
       2. A method according to  claim 1 , wherein
 to form the nitride film on the first sidewall surface of the one of the polysilicon layer and the amorphous silicon layer and bury the element isolation insulating film in the element isolation trench, 
 after the first sidewall surface of the one of the polysilicon layer and the amorphous silicon layer is nitrided, the element isolation insulating film is buried in the element isolation trench. 
 
     
     
       3. A method according to  claim 2 , wherein before nitriding the first sidewall surface of the one of the polysilicon layer and the amorphous silicon layer, an oxide film is formed on the first sidewall surface of the one of the polysilicon layer and the amorphous silicon layer. 
     
     
       4. A method according to  claim 1 , wherein to form the nitride film on the first sidewall surface of the one of the polysilicon layer and the amorphous silicon layer and bury the element isolation insulating film in the element isolation trench,
 after a coating film containing nitrogen is buried in the element isolation trench, the coating film is annealed to convert the coating film into a silicon oxide film and nitride the first sidewall surface of the one of the polysilicon layer and the amorphous silicon layer. 
 
     
     
       5. A method according to  claim 4 , wherein before nitriding the first sidewall surface of the one of the polysilicon layer and the amorphous silicon layer, an oxide film is formed on the first sidewall surface of the one of the polysilicon layer and the amorphous silicon layer. 
     
     
       6. A method according to  claim 4 , wherein a silazane polymer is used as the coating film. 
     
     
       7. A method according to  claim 1 , wherein a nitrogen concentration on the first sidewall surface of the one of the polysilicon layer and the amorphous silicon layer is higher than that in a sidewall of the semiconductor substrate. 
     
     
       8. A method according to  claim 1 , wherein the forming one of the polysilicon layer and the amorphous silicon layer to have a two-layered structure as the floating gate electrode, includes forming a first layer on the tunnel insulating film, and forming a second layer on the first silicon layer and element isolation insulating film after the element isolation insulating film is buried. 
     
     
       9. A method of manufacturing a semiconductor device having a transistor element, comprising:
 forming an element isolation trench on one major surface side of a semiconductor substrate to surround an element formation region; 
 burying a coating film containing nitrogen in the element isolation trench; 
 converting the coating film into a first silicon oxide film to form an element isolation insulating film and a first silicon nitride film by nitriding the semiconductor substrate on a sidewall surface of the element isolation trench and to form a second silicon nitride film on a portion of a sidewall surface of the element formation region; and 
 forming a second silicon oxide film on a surface of the semiconductor substrate in the element formation region in an atmosphere containing radical oxygen after forming the first and second nitride films. 
 
     
     
       10. A method according to  claim 9 , wherein the second silicon oxide film is used as one of a gate insulating film and part of the gate insulating film. 
     
     
       11. A method according to  claim 9 , wherein the coating film is made of silazane polymer. 
     
     
       12. A method according to  claim 9 , wherein the coating film is buried in the element isolation trench after a thermal oxide film is formed on the sidewall surface of the element isolation trench. 
     
     
       13. A method of manufacturing a semiconductor device having a nonvolatile semiconductor memory element with a two-layered gate structure, comprising:
 stacking a tunnel insulating film and one of a polysilicon layer and an amorphous silicon layer serving as a floating gate electrode on one major surface of a semiconductor substrate; 
 selectively etching the one of the polysilicon layer and the amorphous silicon layer, the tunnel insulating film, and the semiconductor substrate using a mask having a pattern corresponding to an element isolation trench so as to form the element isolation trench; 
 forming a nitride film on a sidewall surface of the one of the polysilicon layer and the amorphous silicon layer exposed into the element isolation trench and burying an element isolation insulating film in the element isolation trench; 
 stacking an electrode insulating film and a conductive film serving as a control gate electrode on the element isolation insulating film and the one of the polysilicon layer and the amorphous silicon layer; and 
 selectively etching the conductive film, the electrode insulating film, and the one of the polysilicon layer and the amorphous silicon layer using a mask having a pattern corresponding to the control gate electrode so as to form the control gate electrode and floating gate electrode; 
 wherein forming the nitride film on the sidewall surface of the one of the polysilicon layer and the amorphous silicon layer and burying the element isolation insulating film in the element isolation trench includes, 
 after a coating film containing nitrogen is buried in the element isolation trench, annealing the coating film to convert the coating film into a silicon oxide film and nitride the sidewall surface of the one of the polysilicon layer and the amorphous silicon layer. 
 
     
     
       14. A method of manufacturing a semiconductor device having a nonvolatile semiconductor memory element with a two-layered gate structure, comprising:
 stacking a tunnel insulating film and one of a polysilicon layer and an amorphous silicon layer serving as a floating gate electrode on one major surface of a semiconductor substrate; 
 selectively etching the one of the polysilicon layer and the amorphous silicon layer, the tunnel insulating film, and the semiconductor substrate using a mask having a pattern corresponding to an element isolation trench so as to form the element isolation trench; 
 forming a nitride film on a sidewall surface of the one of the polysilicon layer and the amorphous silicon layer exposed into the element isolation trench and burying an element isolation insulating film in the element isolation trench; 
 stacking an electrode insulating film and a conductive film serving as a control gate electrode on the element isolation insulating film and the one of the polysilicon layer and the amorphous silicon silicon layer; and 
 selectively etching the conductive film, the electrode insulating film, and the one of the polysilicon layer and the amorphous silicon layer using a mask having a pattern corresponding to the control gate electrode so as to form the control gate electrode and floating gate electrode; 
 wherein a nitrogen concentration in the sidewall of the one of the polysilicon layer and the amorphous silicon layer is higher than that in a sidewall of the semiconductor substrate.