Nonvolatile semiconductor memory device

Abstract

The nonvolatile semiconductor memory device includes a memory cell array containing a plurality of nonvolatile memory cells and an initial setup data region in which initial setup data specified to determine operation conditions of the device is to be written. The device further includes a detection circuit which detects turn-on of power. The device further includes a readout circuit which reads out the initial setup data from the initial setup data region of the memory cell array upon detecting power-on by the detection circuit. The device further includes a determination circuit which determines whether the initial setup data read out by the readout circuit is effective or ineffective. The device further includes a setup circuit which sets up the device in an operative-prohibiting status when the initial setup data is determined as ineffective by the determination circuit.

1. A nonvolatile semiconductor memory device operating method comprising:
 detecting turn-on of power; 
 reading out initial setup data in a memory cell array by a readout circuit after detecting turn-on of power; 
 determining whether the initial setup data read out by the readout circuit is effective or ineffective by a determination circuit; and 
 setting up the nonvolatile semiconductor memory device in an operation-prohibiting state when the initial setup data is determined as ineffective by the determination circuit. 
 
   
   
     2. The nonvolatile semiconductor memory device operating method according to  claim 1 , wherein the memory cell array is an electrically programmable NAND type flash memory. 
   
   
     3. The nonvolatile semiconductor memory device operating method according to  claim 1 , wherein when the initial setup data is determined as ineffective, the determination circuit fixes a chip status to a fail status. 
   
   
     4. The nonvolatile semiconductor memory device operating method according to  claim 1 , which uses a control circuit which executes an initial setup operation, the control circuit executing the initial setup operation by causing a data latch circuit to latch the initial setup data when the initial setup data is determined as effective. 
   
   
     5. The nonvolatile semiconductor memory device operating method according to  claim 1 , wherein when the initial setup data is determined as effective, the determination circuit fixes a chip status to a pass status. 
   
   
     6. The nonvolatile semiconductor memory device operating method according to  claim 1 , wherein
 the memory cell array includes a redundancy cell array to be replaced with a defective cell; and 
 the initial setup data includes control data which replaces the defective cell with the redundancy cell array. 
 
   
   
     7. The nonvolatile semiconductor memory device operating method according to  claim 1 , wherein the initial setup data includes control data which controls data write, erase and read operations. 
   
   
     8. The nonvolatile semiconductor memory device operating method according to  claim 1 , wherein
 the initial setup data includes control data which replaces a defective cell with the redundancy cell array and controls data write, erase and read operations, and reference data which confirms the effectiveness of the control data; 
 the determination circuit determines whether the initial setup data is effective or ineffective based on whether or not the control data and the reference data correspond to each other. 
 
   
   
     9. The nonvolatile semiconductor memory device operating method according to  claim 8 , wherein the reference data is complementary to the control data. 
   
   
     10. The nonvolatile semiconductor memory device operating method according to  claim 1 , wherein the memory cell array includes a plurality of planes, and each of the plurality of planes has an initial setup data region established. 
   
   
     11. The nonvolatile semiconductor memory device operating method according to  claim 10 , wherein the same initial setup data is written in each initial setup data region of the plurality of planes; and
 the determination circuit determines whether the initial setup data is effective or ineffective for each initial setup data written in each initial setup data region. 
 
   
   
     12. The nonvolatile semiconductor memory device operating method according to  claim 1 , further comprising:
 setting an interior timer circuit in a nonactive state by setting the nonvolatile semiconductor memory device in an operation-prohibiting state. 
 
   
   
     13. The nonvolatile semiconductor memory device operating method according to  claim 1 , further comprising:
 setting a voltage generation circuit in a nonactive state by a voltage generation circuit setup circuit by setting the nonvolatile semiconductor memory device in an operation-prohibiting state. 
 
   
   
     14. The nonvolatile semiconductor memory device operating method according to  claim 4 , further comprising:
 causing the control circuit to externally output a busy signal until the initial setup operation finishes. 
 
   
   
     15. A nonvolatile semiconductor memory device operating method comprising:
 detecting turn-on of power; 
 reading out initial setup data in a memory cell array after detecting turn-on of power; 
 determining whether the initial setup data is effective or ineffective; and 
 setting up the nonvolatile semiconductor memory device in an operation-prohibiting state when the initial setup data is determined as ineffective. 
 
   
   
     16. The nonvolatile semiconductor memory device operating method according to  claim 15 , wherein the memory cell array is an electrically programmable NAND type flash memory. 
   
   
     17. The nonvolatile semiconductor memory device operating method according to  claim 15 , wherein when the initial setup data is determined as ineffective, a chip status is turned to a fail status. 
   
   
     18. The nonvolatile semiconductor memory device operating method according to  claim 15 , wherein when the initial setup data is determined as effective, a chip status is turned to a pass status. 
   
   
     19. The nonvolatile semiconductor memory device operating method according to  claim 15 , wherein
 the memory cell array includes a redundancy cell array to be replaced with a defective cell; and 
 the initial setup data includes control data which replaces the defective cell with the redundancy cell array. 
 
   
   
     20. The nonvolatile semiconductor memory device operating method according to  claim 15 , wherein the initial setup data includes control data which control data write, erase and read operations. 
   
   
     21. The nonvolatile semiconductor memory device operating method according to  claim 15 , wherein
 the initial setup data includes control data which replaces a defective cell with the redundancy cell array and controls data write, erase and read operations, and reference data which confirms the effectiveness of the control data; 
 the initial setup data is determined whether effective or ineffective based on whether or not the control data and the reference data correspond to each other. 
 
   
   
     22. The nonvolatile semiconductor memory device operating method according to  claim 21 , wherein the reference data is complementary to the control data. 
   
   
     23. The nonvolatile semiconductor memory device operating method according to  claim 15 , wherein the memory cell array includes a plurality of planes, and each of the plurality of planes has an initial setup data region. 
   
   
     24. The Nonvolatile semiconductor memory device operating method according to  claim 23 , wherein the same initial setup data is written in each initial setup data region of the plurality of planes; and
 the initial setup data is determined whether effective or ineffective for each initial setup data written in each initial setup data region. 
 
   
   
     25. The nonvolatile semiconductor memory device operating method according to  claim 15 , further comprising:
 setting an interior timer circuit in a nonactive state by setting the nonvolatile semiconductor memory device in an operation-prohibiting state. 
 
   
   
     26. The nonvolatile semiconductor memory device operating method according to  claim 15 , further comprising:
 setting a voltage generation circuit in a nonactive state by setting the nonvolatile semiconductor memory device in an operation-prohibiting state.