JFET controlled schottky barrier diode

Abstract

A JFET controlled Schottky barrier diode includes a p-type diffusion region integrated into the cathode of the Schottky diode to form an integrated JFET where the integrated JFET provides on-off control of the Schottky barrier diode. The p-type diffusion region encloses a portion of the forward current path of the Schottky barrier diode where the p-type diffusion region forms the gate of the JFET and the enclosed portion of the forward current path forms the channel region of the JFET. By applying a reverse biased potential to the gate of the JEFT with respect to the anode of the Schottky diode, the forward current of the Schottky diode can be pinched off, thereby providing on-off control over the Schottky diode forward current.

1. A JFET controlled Schottky diode comprising:
 a semiconductor layer of N-type conductivity; 
 a first region of N-type conductivity formed in the semiconductor layer, the first region being lightly doped and forming the cathode region of the Schottky diode; 
 a second region of N-type conductivity formed in the semiconductor layer, the second region being heavily doped and being electrically coupled to the first region through the semiconductor layer and one or more diffusion regions formed in the semiconductor layer, the second region forming the cathode terminal of the Schottky diode where a forward current path of the Schottky diode is formed between the first region and the second region; 
 a barrier metal electrode formed on the top surface of the semiconductor layer and above the first region, the barrier metal electrode being in ohmic contact with the first region and thereby forming a Schottky junction with the first region, the barrier metal electrode forming the anode terminal of the Schottky diode; 
 a third region of P-type conductivity formed in the semiconductor layer and enclosing a portion of the forward current path of the Schottky diode between the first region and the second region, the third region forming the gate of the JFET and the enclosed portion of the forward current path forming the channel region of the JFET; and 
 a first metal electrode formed on the top surface of the semiconductor layer and electrically coupled to the third region, the first metal electrode forming a gate terminal of the JFET, 
 wherein the forward current path of the Schottky diode is put in a conducting state by the application of a voltage to the gate terminal relative to the anode terminal that is equal to or greater than the pinch-off voltage of the JFET and the forward current path of the Schottky diode is put in a non-conducting state by the application of a voltage to the gate terminal relative to the anode terminal that is less than the pinch-off voltage of the JFET. 
 
   
   
     2. The JFET controlled Schottky diode of  claim 1 , wherein the forward current path between the first region and the second region has a vertical component relative to the top surface of the semiconductor layer, the third region being disposed to enclose a portion of the vertical component of the forward current path. 
   
   
     3. The JFET controlled Schottky diode of  claim 1 , wherein the forward current path between the first region and the second region has a horizontal component relative to the top surface of the semiconductor layer, the third region being disposed to enclose a portion of the horizontal component of the forward current path. 
   
   
     4. The JFET controlled Schottky diode of  claim 1 , further comprising a second metal electrode formed on the top surface of the semiconductor layer and in ohmic contact with the second region, the second metal electrode forming the cathode terminal of Schottky diode. 
   
   
     5. The JFET controlled Schottky diode of  claim 1 , wherein the semiconductor layer comprises an epitaxial layer of N-type conductivity formed on a semiconductor substrate of P-type conductivity. 
   
   
     6. The JFET controlled Schottky diode of  claim 5 , wherein the first region comprises an N-Well region formed in the epitaxial layer. 
   
   
     7. The JFET controlled Schottky diode of  claim 6 , further comprising:
 a buried layer of N-type conductivity formed partially in the semiconductor substrate and partially in the epitaxial layer, the buried layer being positioned underneath and spaced apart from the N-Well region forming the first region; and 
 a sinker region of N-type conductivity formed in the epitaxial layer, the third region being formed in the sinker region, the sinker region being in contact with and electrically coupled to the buried layer, 
 wherein the forward current path from the first region to the second region comprises a current path from the N-Well, through the epitaxial layer under the N-Well, to the buried layer where the current is collected by the sinker region and provided to the cathode terminal formed by the second region. 
 
   
   
     8. The JFET controlled Schottky diode of  claim 7 , wherein the third region of P-type conductivity comprises:
 a first p-type diffusion region formed in the epitaxial layer and between the N-Well and the buried layer, the first p-type diffusion region extending partially under the N-well to enclose a portion of the forward current path of the Schottky diode that lies in the epitaxial layer between the N-Well and the buried layer; 
 a second p-type diffusion region formed in the epitaxial layer, the second p-type diffusion region being in contact with and electrically coupled to the first p-type diffusion region, 
 a third p-type diffusion region formed on the top surface of the epitaxial layer and in the second p-type diffusion region, the third p-type diffusion region being heavily doped, the first metal electrode being in ohmic contact with the third p-type diffusion region, 
 wherein the forward current path enclosed by the first p-type diffusion region has a first diameter and the pinch-off voltage of the JFET is a function of the first diameter and the doping concentration of the epitaxial layer. 
 
   
   
     9. The JFET controlled Schottky diode of  claim 8 , wherein the first p-type diffusion region extends at least partially into the bottom of the N-well and encloses a portion of the forward current path of the Schottky diode that lies in the bottom of the N-well and in the epitaxial layer between the N-Well and the buried layer, and wherein the pinch-off voltage of the JFET is a function of the first diameter and the doping concentration of the epitaxial layer and the N-Well. 
   
   
     10. The JFET controlled Schottky diode of  claim 8 , wherein the first p-type diffusion region comprises an ISOUP region in a fabrication process, the second p-type diffusion region comprises a P-Well in the fabrication process, and the third region comprises a p+region in the fabrication process. 
   
   
     11. The JFET controlled Schottky diode of  claim 10 , wherein the fabrication process comprises one of a BCD, BiCMOS, Bipolar, or CMOS fabrication process. 
   
   
     12. The JFET controlled Schottky diode of  claim 6 , further comprising:
 a buried layer of N-type conductivity formed partially in the semiconductor substrate and partially in the epitaxial layer, the buried layer being positioned underneath and spaced apart from the N-Well region forming the first region; and 
 a sinker region of N-type conductivity formed in the epitaxial layer, the third region being formed in the sinker region, the sinker region being in contact with and electrically coupled to the buried layer, 
 wherein the forward current path from the first region to the second region comprises a current path from the N-Well, through the epitaxial layer on the sides of the N-Well, to the sinker region directly or to the buried layer where the current is collected by the sinker region, the sinker region providing the current to the cathode terminal formed by the second region. 
 
   
   
     13. The JFET controlled Schottky diode of  claim 12 , wherein the third region of P-type conductivity comprises:
 a first p-type diffusion region formed in the epitaxial layer and between the N-Well and the buried layer, the first p-type diffusion region extending across the entire bottom surface of the N-well and having a first portion that extends outside of the N-well; 
 a second p-type diffusion region formed in the epitaxial layer and being positioned above of and spaced apart from the first portion of the first p-type diffusion region, the second p-type diffusion region being electrically coupled to the first p-type diffusion region; and 
 a third p-type diffusion region formed on the top surface of the epitaxial layer and in the second p-type diffusion region, the third p-type diffusion region being heavily doped, the first metal electrode being in ohmic contact with the third p-type diffusion region, 
 wherein the first p-type diffusion region and the second p-type diffusion region encloses a portion of the forward current path of the Schottky diode that lies in the epitaxial layer from the sides of the N-Well to the sinker region and the buried layer, and wherein the forward current path enclosed by the first and second p-type diffusion regions has a first diameter and the pinch-off voltage of the JFET is a function of the first diameter and the doping concentration of the epitaxial layer. 
 
   
   
     14. The JFET controlled Schottky diode of  claim 13 , wherein the first p-type diffusion region comprises an ISOUP region in a fabrication process, the second p-type diffusion region comprises a P-drift region in the fabrication process, and the third region comprises a p+ region in the fabrication process. 
   
   
     15. The JFET controlled Schottky diode of  claim 14 , wherein the fabrication process comprises one of a BCD, BiCMOS, Bipolar, or CMOS fabrication process.