Image display apparatus

Abstract

An image display apparatus comprises a line buffer unit which stores binary image data, the binary image data being divided into a plurality of line portion data, each line portion data having a fixed length. Pattern matching units are connected in parallel with the line buffer unit and receives the line portion data respectively, each pattern matching unit determining whether an input pattern of a related line portion data matches with one of reference patterns. When the match occurs each pattern matching unit outputs a truth signal indicating the value one, and otherwise each pattern matching unit outputs a falseness signal indicating the value zero. A judgment unit receives the truth or falseness signals from the pattern matching units and determines how many times the match with respect to one of the reference patterns occurs in succession based on the received signals, the judgment unit encoding lengths of runs for the line portion data having the fixed length based on results of the determination and storing the codes in the video memory.

1. An information processing apparatus which encodes data and stores the encoded data into a memory, and reads the data from the memory and decodes the read data, comprising:
 a plurality of pattern matching units connected in parallel, each pattern matching unit determining whether an input pattern of a related line portion data matches with a corresponding one of a plurality of reference patterns, wherein, when the match occurs each pattern matching unit outputs a truth signal indicating a value one, and otherwise each pattern matching unit outputs a false signal indicating a value zero; and 
 a judgment unit receiving the truth or false signals from the plurality of pattern matching units and determining how many times the match with respect to one of the plurality of reference patterns occurs in succession, based on the received signals, the judgment unit encoding lengths of runs for the plurality of line portion data having the fixed length based on results of the determination and storing the codes in the memory. 
 
   
   
     2. The information processing apparatus according to  claim 1  further comprising a reference pattern changing unit changing setting of the plurality of reference patterns, used by the plurality of pattern matching units when performing the pattern matching, to a predetermined setting. 
   
   
     3. The information processing apparatus according to  claim 2  wherein the reference pattern changing unit comprises a reference pattern register storing a desired reference pattern that is supplied to one of the plurality of pattern matching units. 
   
   
     4. The information processing apparatus according to  claim 1  further comprising an identifying data inserting unit inserting an identifying data, which discriminates a run-length code and a bit-map data, to each of the codes output from the judgment unit. 
   
   
     5. An information processing apparatus which encodes data and stores the encoded data into a memory, and reads the data from the memory and decodes the read data, comprising:
 a line buffer unit storing binary data which is received at an input thereof, the binary data being divided into a plurality of line portion data, each line portion data having a fixed length; 
 a plurality of pattern matching units connected in parallel with the line buffer unit and receiving the plurality of line portion data respectively, each pattern matching unit determining whether an input pattern of a related line portion data matches with a corresponding one of a plurality of reference patterns, wherein, when the match occurs each pattern matching unit outputs a truth signal indicating a value one, and otherwise each pattern matching unit outputs a false signal indicating a value zero; and 
 a sequential logic circuit receiving the truth or false signals from the plurality of pattern matching units and determining how many times the match with respect to one of the plurality of reference patterns occurs in succession, based on the received signals, the sequential logic circuit encoding lengths of runs for the plurality of line portion data having the fixed length based on results of the determination and storing the codes in the memory. 
 
   
   
     6. The information processing apparatus according to  claim 5  further comprising a reference pattern changing unit changing setting of the plurality of reference patterns, used by the plurality of pattern matching units when performing the pattern matching, to a predetermined setting. 
   
   
     7. The information processing apparatus according to  claim 6  wherein the reference pattern changing unit comprises a reference pattern register storing a desired reference pattern that is supplied to one of the plurality of pattern matching units. 
   
   
     8. The information processing apparatus according to  claim 5  further comprising an identifying data inserting unit inserting an identifying data, which discriminates a run-length code and a bit-map data, to each of the codes output from the judgment unit. 
   
   
     9. An information processing method which encodes data and stores the encoded data into a memory, and reads the data from the memory and decodes the read data, comprising:
 determining, by each of a plurality of pattern matching units connected in parallel, whether an input pattern of a related line portion data matches with a corresponding one of a plurality of reference patterns, wherein, when the match occurs each pattern matching unit outputs a truth signal indicating a value one, and otherwise each pattern matching unit outputs a false signal indicating a value zero; and 
 receiving the truth or false signals from the plurality of pattern matching units and determining how many times the match with respect to one of the plurality of reference patterns occurs in succession, based on the received signals, including encoding lengths of runs for the plurality of line portion data having the fixed length based on results of the determination and storing the codes in the memory. 
 
   
   
     10. The information processing method according to  claim 9  further comprising changing setting of the plurality of reference patterns, used by the plurality of pattern matching units when performing the pattern matching, to a predetermined setting. 
   
   
     11. The information processing method according to  claim 10  wherein the changing setting comprises storing a desired reference pattern that is supplied to one of the plurality of pattern matching units. 
   
   
     12. The information processing method according to  claim 9  further comprising inserting an identifying data, which discriminates a run-length code and a bit-map data, to each of the output codes. 
   
   
     13. An image display apparatus which encodes data and stores the encoded data into a memory, and reads the data from the memory and decodes the read data, comprising:
 a plurality of pattern matching units connected in parallel, each pattern matching unit determining whether an input pattern of a related line portion data matches with a corresponding one of a plurality of reference patterns, wherein, when the match occurs each pattern matching unit outputs a truth signal indicating a value one, and otherwise each pattern matching unit outputs a false signal indicating a value zero; and 
 a judgment unit receiving the truth or false signals from the plurality of pattern matching units and determining how many times the match with respect to one of the plurality of reference patterns occurs in succession, based on the received signals, the judgment unit encoding lengths of runs for the plurality of line portion data having the fixed length based on results of the determination and storing the codes in the memory.