Magnetoelectronic devices utilizing protective capping layers and methods of fabricating the same

Abstract

Magnetoelectronic device structures and methods for fabricating the same are provided. One method comprises forming a first and a second conductor. The first conductor is electrically coupled to an interconnect stack. A first insulating layer is deposited overlying the first conductor and the second conductor. A via is etched to substantially expose the first conductor. A protective capping layer is deposited by electroless deposition within the via and is electrically coupled to the first conductor. A magnetic memory element layer is formed within the via and overlying the second insulating layer and the second conductor.

What is claimed is: 
     
       1. A method for fabricating a magnetoelectronic device, the method comprising:
 forming a first conductor and a second conductor, wherein said first conductor is electrically coupled to an interconnect stack; 
 depositing a first insulating layer overlying said first conductor and said second conductor; 
 etching a via within said first insulating layer to substantially expose said first conductor; 
 depositing by electroless deposition a protective capping layer within said via overlying said first conductor, said protective capping layer electrically coupled to said first conductor; and 
 forming a magnetic memory element layer within said via and overlying said first insulating layer and said second conductor. 
 
     
     
       2. The method for fabricating a magnetoelectronic device of  claim 1 , wherein the step of forming a first conductor and a second conductor comprises the step of forming said first conductor and said second conductor of copper. 
     
     
       3. The method for fabricating a magnetoelectronic device of  claim 1 , wherein the step of forming a first conductor and a second conductor comprise:
 fabricating an interconnect stack that is disposed at least partially within a layer of dielectric material; 
 depositing a second insulating layer overlying said interconnect stack and said layer of dielectric material; 
 etching a first trench and a second trench within said second insulating layer, said first trench exposing said interconnect stack; and 
 forming said first conductor in said first trench and said second conductor in said second trench. 
 
     
     
       4. The method for fabricating a magnetoelectronic device of  claim 3 , the method further comprising the step of forming a cladding layer within said first trench and said second trench before the step of forming said first conductor and said second conductor. 
     
     
       5. The method for fabricating a magnetoelectronic device of  claim 1 , wherein the step of depositing a protective capping layer comprises depositing a material layer comprising at least one selected from the group consisting of palladium, platinum, ruthenium, cobalt, nickel, tungsten, alloys of palladium, alloys of platinum, alloys of ruthenium, alloys of cobalt, alloys of nickel, and alloys of tungsten. 
     
     
       6. The method for fabricating a magnetoelectronic device of  claim 1 , further comprising the step of depositing a first conductive layer within said via and overlying said first insulating layer and said second conductor, which step is performed before the step of forming a magnetic memory element layer. 
     
     
       7. A method for fabricating a magnetoelectronic device, the method comprising:
 forming a first conductor and a second conductor, wherein said first conductor is electrically coupled to an interconnect stack; 
 depositing a first protective capping layer overlying said first conductor and a second protective capping layer overlying said second conductor, said first and second protective capping layers deposited using an electroless deposition process; 
 depositing a first insulating layer overlying said first and said second protective capping layers; 
 etching a via within said first insulating layer to expose said first protective capping layer; and 
 forming a magnetic memory element layer within said via and overlying said first insulating layer and said second conductor. 
 
     
     
       8. The method for fabricating a magnetoelectronic device of  claim 7 , wherein the step of forming a first conductor and a second conductor comprises the step of forming said first conductor and said second conductor of copper. 
     
     
       9. The method for fabricating a magnetoelectronic device of  claim 7 , wherein the step of forming a first conductor and a second conductor comprise:
 fabricating an interconnect stack that is disposed at least partially within a layer of dielectric material; 
 depositing a second insulating layer overlying said interconnect stack and said layer of dielectric material; 
 etching a first trench and a second trench within said second insulating layer, said first trench exposing said interconnect stack; and 
 forming said first conductor in said first trench and said second conductor in said second trench. 
 
     
     
       10. The method for fabricating a magnetoelectronic device of  claim 9 , the method further comprising the step of forming a cladding layer within said first trench and said second trench before the step of forming said first conductor and said second conductor. 
     
     
       11. The method for fabricating a magnetoelectronic device of  claim 7 , wherein the step of depositing a protective capping layer comprises depositing a material layer comprising at least one selected from the group consisting of palladium, platinum, ruthenium, alloys of palladium, alloys of platinum, alloys of ruthenium, and nickel phosphorous. 
     
     
       12. The method for fabricating a magnetoelectronic device of  claim 7 , wherein the step of depositing a protective capping layer comprises the step of depositing a protective capping layer to a thickness of no less than about 20 nanometers. 
     
     
       13. The method for fabricating a magnetoelectronic device of  claim 7 , further comprising the step of depositing a first conductive layer within said via and overlying said first insulating layer and said second conductor, which step is performed before the step of forming a magnetic memory element layer. 
     
     
       14. The method for fabricating a magnetoelectronic device of  claim 13 , further comprising the step of etching said magnetic memory element layer so that a memory element is disposed overlying said second conductor, is magnetically coupled to said second conductor, and is electrically coupled to said first conductor by said first conductive layer and said protective capping layer. 
     
     
       15. A magnetoelectronic device comprising:
 a first conductor and a second conductor, wherein said first conductor is electrically coupled to an interconnect stack; 
 a first protective capping layer disposed overlying said first conductor and electrically coupled to said first conductor; 
 a first insulating layer disposed overlying said second conductor; 
 a first conductive electrode layer disposed overlying said first insulating layer and said second conductor and electrically coupled to said first conductor through said first protective capping layer; and 
 a magnetic memory element disposed overlying said first conductive electrode layer, said second insulating layer, and said second conductor, wherein said magnetic memory element is magnetically coupled to said second conductor and is electrically coupled to said first conductor via said first conductive electrode layer and said first protective capping layer. 
 
     
     
       16. The magnetoelectronic device structure of  claim 15 , wherein said first conductor and said second conductor comprise copper. 
     
     
       17. The magnetoelectronic device structure of  claim 15 , wherein said protective capping layer comprises at least material selected from the group consisting of palladium, platinum, ruthenium, cobalt, nickel, tungsten, alloys of palladium, alloys of platinum, alloys of ruthenium, alloys of cobalt, alloys of nickel, and alloys of tungsten. 
     
     
       18. The magnetoelectronic device structure of  claim 15 , further comprising a second protective capping layer disposed overlying said second conductor. 
     
     
       19. The magnetoelectronic device structure of  claim 18 , wherein said protective capping layer comprises at least one material selected from the group consisting of palladium, platinum, ruthenium, alloys of palladium, alloys of platinum, alloys of ruthenium, and nickel phosphorous. 
     
     
       20. The magnetoelectronic device structure of  claim 15 , wherein said first protective capping layer has a thickness of no less than about 20 nanometers.