Dynamic input/output: configurable data bus for optimizing data throughput

Abstract

A dynamic I/O configuration and protocol includes a configurable data bus for optimizing data throughput. The configurable data bus includes multiple bi-directional data buses between a memory device and a controller to maximize the data transfer efficiency of operation sequences and thereby optimize data throughput to and from the memory device. Each of the bi-directional data buses are configured for utilization in both read operations from and write operations to the memory device. Using control input signal lines, the controller specifies a current operation to be performed and the data bus to be used to perform the current operation. The specific instructions that are provided from the controller to the memory device depend on the particular operation sequence being performed.

1. A method of reading data from and writing data to a memory device over a bus structure including a plurality of signal lines, comprising:
 a. grouping the plurality of signal lines into two or more bi-directional and reconfigurable groups; and 
 b. transmitting data to and from the memory device over the groups of signal lines by specifying a selected group of the groups of signal lines and a current operation. 
 
   
   
     2. The method as claimed in  claim 1  wherein the selected group and the current operation are specified over operation control input signal lines. 
   
   
     3. The method as claimed in  claim 2  wherein the operation control input signal lines are provided to the memory device from a controller. 
   
   
     4. The method as claimed in  claim 1  wherein the memory device is an SRAM. 
   
   
     5. The method as claimed in  claim 1  wherein transmitting includes alternating groups of signal lines to complete a sequence of operations. 
   
   
     6. The method as claimed in  claim 1  wherein the current operation includes one of a read operation, a write operation and a deselect operation. 
   
   
     7. The method as claimed in  claim 6  wherein transmitting includes initiating read and write operations alternately between groups of signal lines except if:
 a. a sequence of two or more consecutive read operations is followed immediately by a write operation, then a last read operation in the sequence is initiated to a same group of signal lines as a second to last read operation in the sequence; and 
 b. a sequence of a read operation followed immediately by two or more consecutive write operations, then a second write operation in the sequence is initiated to a same group of signal lines as a first write operation in the sequence. 
 
   
   
     8. A method of reading data from and writing data to a memory device over a bus structure including a plurality of signal lines, comprising:
 a. grouping the plurality of signal lines into two or more bi-directional and reconfigurable groups, wherein each group of signal lines is capable of performing both read and write operations; 
 b. specifying control signals for a current operation, the control signals including a selected one of the groups of signal lines and the current operation; and 
 c. communicating data for the current operation over the selected group of signal lines in a direction dependent upon the current operation. 
 
   
   
     9. The method as claimed in  claim 8  wherein the control signals are specified over operation control input signal lines. 
   
   
     10. The method as claimed in  claim 9  wherein the operation control input signal lines are provided to the memory device from a controller. 
   
   
     11. The method as claimed in  claim 8  wherein the memory device is an SRAM. 
   
   
     12. The method as claimed in  claim 8  wherein communicating includes alternating groups of signal lines to complete a sequence of operations. 
   
   
     13. The method as claimed in  claim 8  wherein the current operation includes one of a read operation, a write operation and a deselect operation. 
   
   
     14. The method as claimed in  claim 13  wherein communicating includes initiating read and write operations alternately between groups of signal lines except if:
 a. a sequence of two or more consecutive read operations is followed immediately by a write operation, then a last read operation in the sequence is initiated to a same group of signal lines as a second to last read operation in the sequence; and 
 b. a sequence of a read operation followed immediately by two or more consecutive write operations, then a second write operation in the sequence is initiated to a same group of signal lines as a first write operation in the sequence. 
 
   
   
     15. A bus structure configured for reading data from and writing data to a memory device, comprising n data signal lines, grouped into a plurality of bidirectional and reconfigurable groups. 
   
   
     16. The bus structure as claimed in  claim 15  wherein each of the groups comprises m data signal lines. 
   
   
     17. The bus structure as claimed in  claim 15  further comprising a plurality of operation control signal lines for communicating operation control signals specifying a selected one of the groups and a current operation. 
   
   
     18. The bus structure as claimed in  claim 17  wherein the current operation includes one of a read operation, a write operation and a deselect operation. 
   
   
     19. The bus structure as claimed in  claim 15  wherein the memory device is an SRAM. 
   
   
     20. The bus structure as claimed in  claim 15  wherein each of the groups of data signal lines are capable of performing both read and write operations. 
   
   
     21. A memory device comprising an interface configured for coupling to a plurality of bidirectional and reconfigurable data signal lines and a plurality of operation control signal lines, wherein the data signal lines are configured for grouping into a plurality of groups, each of the groups of data signal lines capable of performing both read and write operations, and further wherein operation control signals are received on the operation control signal lines specifying a selected one of the groups of data signal lines and a current operation. 
   
   
     22. The memory device as claimed in  claim 21  wherein the operation control signal lines are provided to the memory device from a controller. 
   
   
     23. The memory device as claimed in  claim 21  wherein the memory device is an SRAM. 
   
   
     24. The memory device as claimed in  claim 21  wherein the current operation includes one of a read operation, a write operation and a deselect operation. 
   
   
     25. A memory device comprising:
 a. a data interface configured for coupling to a plurality of bidirectional and reconfigurable data signal lines, wherein the data signal lines are configured for grouping into a plurality of groups, each of the groups of data signal lines capable of performing both read and write operations; and 
 b. a control interface configured for coupling to a plurality of operation control signal lines for receiving operation control signals, wherein the operation control signals specify a selected one of the groups of data signal lines and a current operation. 
 
   
   
     26. The memory device as claimed in  claim 25  wherein the operation control signal lines are provided to the memory device from a controller. 
   
   
     27. The memory device as claimed in  claim 25  wherein the memory device is an SRAM. 
   
   
     28. The memory device as claimed in  claim 25  wherein the current operation includes one of a read operation, a write operation and a deselect operation. 
   
   
     29. A memory system comprising:
 a. a plurality of bidirectional and reconfigurable data signal lines configured for grouping into a plurality of groups, each of the groups of data signal lines capable of performing both read and write operations; 
 b. a plurality of operation control signal lines for transmitting operation control signals; 
 c. a memory controller including:
 i. a controller data interface coupled to the plurality of data signal lines for transmitting and receiving data over the data signal lines; and 
 ii. a controller control interface coupled to the plurality of operation control signal lines for transmitting the operation control signals; and 
 
 d. a memory device including:
 i. a device data interface coupled to the plurality of data signal lines for performing both read and write operations over the data signal lines: and 
 ii. a device control interface coupled to the plurality of operation control signal lines for receiving the operation control signals from the controller control interface, wherein the operation control signals specify a selected one of the groups of data signal lines and a current operation. 
 
 
   
   
     30. The memory system as claimed in  claim 29  wherein the memory device is an SRAM. 
   
   
     31. The memory system as claimed in  claim 29  wherein the current operation includes one of a read operation, a write operation and a deselect operation.