High bandwidth phase locked loop (PLL)

Abstract

A phase locked loop (PLL) is provided. In one implementation, the PLL includes a feedback loop having a frequency multiplier and an integer divider to generate a divided signal. The PLL includes a re-sampling circuit operable to re-sample one or more digital pulses of the divided signal using one or more phase signals if a multiplication factor of the frequency multiplier does not divide evenly into the integer divisor.

1. A phase locked loop, comprising:
 a feedback loop, the feedback loop including,
 an integer divider operable to divide a feedback loop signal in accordance with an integer divisor and produce a divided signal having one or more digital pulses; 
 a frequency multiplier operable to multiply the divided signal by a multiplication factor, including inserting one or more additional digital pulses into the divided signal to generate a multiplied signal; and 
 a re-sampling circuit operable to re-sample one or more of the additional digital pulses inserted into the divided signal if the multiplication factor does not divide evenly into the integer divisor. 
 
 
   
   
     2. The phase locked loop of  claim 1 , wherein the re sampling circuit is operable to re-sample one or more of the additional digital pulses inserted into the divided signal using one or more phase signals, each of the phase signals being delayed with respect to each other. 
   
   
     3. The phase locked loop of  claim 2 , further comprising a multiphase voltage controlled oscillator operable to generate the one or more phase signals. 
   
   
     4. The phase locked loop of  claim 2 , wherein the re sampling circuit comprises a flip-flop that is clocked using one or more of the phase signals to re-sample one or more of the additional digital pulses. 
   
   
     5. The phase locked loop of  claim 4 , wherein the re sampling circuit further comprises a multiplexer that is operable to select a given phase signal to clock the flip flop. 
   
   
     6. The phase locked loop of  claim 4 , wherein the re sampling circuit further comprises a multiplexer that is operable to be controlled by a least significant bit of a binary value of the integer divisor for re-sampling one or more of the additional digital pulses. 
   
   
     7. The phase locked loop of  claim 6 , wherein the re sampling circuit further comprises an OR gate operable to insert one or more of the additional digital pulses into the divided signal. 
   
   
     8. The phase locked loop of  claim 3 , further comprising a phase-frequency detector operable to compare a reference signal to the multiplied signal, and generate an error signal corresponding to a frequency difference between the reference signal and the multiplied signal. 
   
   
     9. The phase locked loop of  claim 8 , further comprising a charge pump operable to convert the error signal into a charge pump output signal. 
   
   
     10. The phase locked loop of  claim 9 , further comprising a loop filter operable to smooth the charge pump output signal and generate a voltage controlled oscillator control signal to control a frequency of an output signal of the multiphase voltage controlled oscillator. 
   
   
     11. The phase locked loop of  claim 10 , further comprising a programmable divider operable to divide the frequency of the output signal of the multiphase voltage controlled oscillator. 
   
   
     12. A method comprising:
 dividing a feedback loop signal in accordance with an integer divisor and generating a divided signal having one or more digital pulses; 
 multiplying the divided signal by a multiplication factor, including inserting one or more additional digital pulses into the divided output signal to generate a multiplied signal; and 
 re-sampling one or more of the additional digital pulses inserted into the divided signal if the multiplication factor does not divide evenly into the integer divisor. 
 
   
   
     13. The method of  claim 12 , wherein re-sampling one or more of the additional digital pulses includes re-sampling one or more of the additional digital pulses inserted into the divided signal using one or more phase signals, each of the phase signals being delayed with respect to each other. 
   
   
     14. The method of  claim 13 , wherein one or more of the phase signals are generated by a multiphase voltage controlled oscillator. 
   
   
     15. The method of  claim 13 , wherein re-sampling one or more of the additional digital pulses includes clocking a flip-flop using one or more of the phase signals. 
   
   
     16. The method of  claim 15 , wherein re-sampling one or more of the additional digital pulses further includes selecting a given phase signal to clock the flip-flop using a multiplexer. 
   
   
     17. The method of  claim 15 , further comprising using a least significant bit of a binary value of the integer divisor to control a multiplexer for re-sampling one or more of the additional digital pulses. 
   
   
     18. The method of  claim 17 , further comprising inserting one or more of the additional digital pulses into the divided signal using an OR gate. 
   
   
     19. The method of  claim 14 , further comprising comparing a reference signal to the multiplied signal, and generating an error signal corresponding to a frequency difference between the reference signal and the multiplied signal. 
   
   
     20. The method of  claim 19 , further comprising converting the error signal into a charge pump output signal. 
   
   
     21. The method of  claim 20 , further comprising smoothing the charge pump output signal and generating a voltage controlled oscillator control signal to control a frequency of an output signal of the multiphase voltage controlled oscillator. 
   
   
     22. The method of  claim 21 , further comprising dividing the frequency of the output signal of the multiphase voltage controlled oscillator. 
   
   
     23. A disk drive system, comprising:
 a read/write head configured to sense changes in magnetic flux on a surface of a disk according to a control signal supplied by a phase locked loop (PLL) and generate a corresponding analog signal, the PLL including,
 an integer divider operable to divide a feedback loop signal in accordance with an integer divisor and produce a divided signal having one or more digital pulses; 
 a frequency multiplier operable to multiply the divided signal by a multiplication factor, including inserting one or more additional digital pulses into the divided signal to generate a multiplied signal; and 
 a re-sampling circuit operable to re-sample one or more of the additional digital pulses inserted into the divided signal if the multiplication factor does not divide evenly into the integer divisor; 
 the disk drive system further comprising a preamplifier configured to amplify the analog signal; and 
 a read channel configured to receive the amplified analog signal and generate a digital read signal based on the amplified analog signal. 
 
 
   
   
     24. The disk drive system of  claim 23 , wherein the re sampling circuit is operable to re-sample one or more of the additional digital pulses inserted into the divided signal using one or more phase signals, each of the phase signals being delayed with respect to each other. 
   
   
     25. The disk drive system of  claim 24 , wherein the PLL further includes a multiphase voltage controlled oscillator operable to generate the one or more phase signals. 
   
   
     26. The disk drive system of  claim 24 , wherein the re sampling circuit comprises a flip-flop that is clocked using one or more of the phase signals to re-sample one or more of the additional digital pulses. 
   
   
     27. The disk drive system of  claim 26 , wherein the re sampling circuit further comprises a multiplexer that is operable to select a given phase signal to clock the flip flop. 
   
   
     28. The disk drive system of  claim 26 , wherein the re sampling circuit further comprises a multiplexer that is operable to be controlled by a least significant bit of a binary value of the integer divisor for re-sampling one or more of the additional digital pulses. 
   
   
     29. The disk drive system of  claim 28 , wherein the re sampling circuit further comprises an OR gate operable to insert one or more of the additional digital pulses into the divided signal. 
   
   
     30. The disk drive system of  claim 25 , wherein the PLL further includes a phase-frequency detector operable to compare a reference signal to the multiplied signal, and generate an error signal corresponding to a frequency difference between the reference signal and the multiplied signal. 
   
   
     31. The disk drive system of  claim 30 , wherein the PLL further includes a charge pump operable to convert the error signal into a charge pump output signal. 
   
   
     32. The disk drive system of  claim 31 , wherein the PLL further includes a loop filter operable to smooth the charge pump output signal and generate a voltage controlled oscillator control signal to control a frequency of an output signal of the multiphase voltage controlled oscillator. 
   
   
     33. The disk drive system of  claim 32 , wherein the PLL further includes a programmable divider operable to divide the frequency of the output signal of the multiphase voltage controlled oscillator. 
   
   
     34. A phase locked loop, comprising:
 feedback means including,
 means for dividing a feedback loop signal in accordance with an integer divisor and producing a divided signal having one or more digital pulses; 
 means for multiplying the divided signal by a multiplication factor, including inserting one or more additional digital pulses into the divided signal and generating a multiplied signal; and 
 means for re-sampling one or more of the additional digital pulses inserted into the divided signal if the multiplication factor does not divide evenly into the integer divisor. 
 
 
   
   
     35. The phase locked loop of  claim 34 , wherein the means for re-sampling is operable to re-sample one or more of the additional digital pulses inserted into the divided signal using one or more phase signals, each of the phase signals being delayed with respect to each other. 
   
   
     36. The phase locked loop of  claim 35 , further comprising generating means for generating the one or more phase signals. 
   
   
     37. The phase locked loop of  claim 35 , wherein the means for re-sampling is clocked using one or more of the phase signals for re-sampling one or more of the additional digital pulses. 
   
   
     38. The phase locked loop of  claim 37 , wherein the means for re-sampling further comprises selector means for selecting a given phase signal to clock the means for re-sampling. 
   
   
     39. The phase locked loop of  claim 37 , wherein the means for re-sampling further comprises selector means that is operable to be controlled by a least significant bit of a binary value of the integer divisor for re-sampling one or more of the additional digital pulses. 
   
   
     40. The phase locked loop of  claim 39 , wherein the means for re-sampling further comprises means for inserting one or more of the additional digital pulses into the divided signal. 
   
   
     41. The phase locked loop of  claim 36 , further comprising means for comparing a reference signal to the multiplied signal, and generating an error signal corresponding to a frequency difference between the reference signal and the multiplied signal. 
   
   
     42. The phase locked loop of  claim 41 , further comprising means for converting the error signal into a charge pump output signal. 
   
   
     43. The phase locked loop of  claim 42 , further comprising means for smoothing the charge pump output signal and generating a control signal to control a frequency of an output signal of the generating means. 
   
   
     44. The phase locked loop of  claim 43 , further comprising means for dividing the frequency of the output signal of the generating means. 
   
   
     45. A disk drive system, comprising:
 sensing means for sensing changes in magnetic flux on a surface of a disk according to a control signal supplied by a phase locking means and generating a corresponding analog signal, the phase locking means including,
 dividing means for dividing a feedback loop signal in accordance with an integer divisor and producing a divided signal having one or more digital pulses; 
 multiplying means for multiplying the divided signal by a multiplication factor, 
 
 including inserting one or more additional digital pulses into the divided signal and generating a multiplied signal; and
 re-sampling means for re-sampling one or more of the additional digital pulses inserted into the divided signal if the multiplication factor does not divide evenly into the integer divisor; 
 
 the disk drive system further comprising means for amplifying the analog signal; and 
 means for receiving the amplified analog signal and generating a digital read signal based on the amplified analog signal. 
 
   
   
     46. The disk drive system of  claim 45 , wherein the re sampling means is operable to re-sample one or more of the additional digital pulses inserted into the divided signal using one or more phase signals, each of the phase signals being delayed with respect to each other. 
   
   
     47. The disk drive system of  claim 46 , wherein the phase locking means further includes generating means for generating the one or more phase signals. 
   
   
     48. The disk drive system of  claim 46 , wherein the re sampling means is clocked using one or more of the phase signals for re-sampling one or more of the additional digital pulses. 
   
   
     49. The disk drive system of  claim 48 , wherein the re sampling means further comprises selector means for selecting a given phase signal to clock the means for re sampling. 
   
   
     50. The disk drive system of  claim 48 , wherein the re sampling means further comprises selector means that is operable to be controlled by a least significant bit of a binary value of the integer divisor for re-sampling one or more of the additional digital pulses. 
   
   
     51. The disk drive system of  claim 50 , wherein the re sampling means further comprises means for inserting one or more of the additional digital pulses into the divided signal. 
   
   
     52. The disk drive system of  claim 47 , wherein the phase locking means further includes means for comparing a reference signal to the multiplied signal, and generating an error signal corresponding to a frequency difference between the reference signal and the multiplied signal. 
   
   
     53. The disk drive system of  claim 52 , wherein the phase locking means further includes means for converting the error signal into a charge pump output signal. 
   
   
     54. The disk drive system of  claim 53 , wherein the phase locking means further includes means for smoothing the charge pump output signal and generating a control signal to control a frequency of an output signal of the generating means. 
   
   
     55. The disk drive system of  claim 54 , wherein the phase locking means further includes programmable means for dividing the frequency of the output signal of the generating means.