Automatic generation of hardware description language code for complex polynomial functions

Abstract

An apparatus and method of implementing a circuit representing a complex polynomial equation in a hardware description language (HDL) for implementing an ASIC (Application Specific Integrated Circuit) is provided. A serial circuit representing the complex polynomial equation is implemented in a software program. The serial circuit implementation is simulated to produce a plurality of parallel equations that are mapped into HDL with ASCII strings. In one embodiment, the complex polynomial equation is a Bose-Chaudhuri-Hocquenghem (BCH) code utilized in forward error correction circuitry.

1. A method for implementing a circuit representing a complex polynomial equation in a hardware description language comprising:
 implementing a serial circuit representing the complex polynomial equation in a software program; wherein implementing the serial circuit includes 
 storing a plurality of ASCII strings in each of a plurality of storage elements, wherein the plurality of ASCII strings represent a plurality of initial values of the serial circuit, 
 storing one or more ASCII strings in each of one or more data structures wherein the one or more ASCII strings represent one or more mathematical operations in the serial circuit, and 
 simulating the serial circuit to produce a plurality of parallel equations, wherein simulating the serial circuit includes 
 simulating the serial circuit for a plurality of cycles as required to produce one output represented by the plurality of parallel equations. 
 
   
   
     2. The method as recited in  claim 1 , wherein storing the one or more ASCII strings comprises:
 storing an ASCII string “XOR” for each addition operation in the serial circuit; and 
 storing an ASCII string “AND” for each multiplication operation in the serial circuit. 
 
   
   
     3. The method as recited in  claim 1 , wherein the complex polynomial equation is a Bose-Chaudhuri-Hocquenghem (BCH) code utilized in forward error correction circuitry. 
   
   
     4. The method as recited in  claim 1 , further comprising:
 writing the plurality of parallel equations to an output file; 
 removing initial register values from each of the parallel equations; 
 adding a feedback value to each of the parallel equations; and 
 merging the parallel equations into a hardware description language (HDL) code file. 
 
   
   
     5. The method as recited in  claim 4 , further comprising:
 manufacturing an application specific integrated circuit from the HDL code file. 
 
   
   
     6. A method for implementing a circuit representing a complex polynomial equation in an ASIC (Application Specific Integrated Circuit) comprising:
 producing one or more parallel equations in a hardware description language, wherein the producing comprises simulating a serial circuit; and 
 merging the one or more parallel equations into a hardware description language implementation of a Galois Field circuit. 
 
   
   
     7. The method as recited in  claim 6 , wherein producing the one or more parallel equations comprises:
 implementing the serial circuit representing the complex polynomial equation in a software program; and 
 simulating the serial circuit to produce the one or more parallel equations. 
 
   
   
     8. The method as recited in  claim 7 , wherein simulating the serial circuit comprises:
 executing the serial circuit for a plurality of cycles as required to produce one output represented by the plurality of parallel equations. 
 
   
   
     9. The method as recited in  claim 7 , wherein implementing the serial circuit comprises:
 storing a plurality of ASCII strings in each of a plurality of storage elements, wherein the plurality of ASCII strings represent a plurality of initial values of the serial circuit; and 
 storing one or more ASCII strings in each of one or more data structures wherein the one or more ASCII strings represent one or more mathematical operations in the serial circuit. 
 
   
   
     10. The method as recited in  claim 9 , wherein storing the one or more ASCII strings in each of one or more data structures comprises:
 storing an ASCII string “XOR” for each addition operation the serial circuit; and 
 storing an ASCII string “AND” for each multiplication operation in the serial circuit. 
 
   
   
     11. The method as recited in  claim 6 , further comprising:
 synthesizing the hardware description language description implementation into a gate level implementation; and 
 manufacturing the ASIC from the gate level implementation. 
 
   
   
     12. The method as recited in  claim 11 , further comprising:
 simulating the gate level implementation to verify accurate design implementation. 
 
   
   
     13. The method as recited in  claim 6 , wherein the complex polynomial equation is a Bose-Chaudhuri-Hocquenghem (BCH) code utilized in forward error correction circuitry. 
   
   
     14. The method as recited in  claim 6 , wherein merging the one or more parallel equations into a hardware description language implementation of a Galois Field circuit comprises:
 removing initial register values from each of the parallel equations; and 
 adding a feedback value to each of the parallel equations. 
 
   
   
     15. An apparatus for implementing complex polynomial equation mathematics in a hardware description language comprising:
 means for implementing a serial circuit representing the complex polynomial equation in a software program; wherein the means for implementing the serial circuit includes
 means for storing a plurality of ASCII strings in each of a plurality of storage elements, wherein the plurality of ASCII strings represent a plurality of initial values of the serial circuit, 
 means for storing one or more ASCII strings in each of one or more data structures wherein the one or more ASCII strings represent one or more mathematical operations in the serial circuit, and 
 
 means for simulating the serial circuit to produce a plurality of parallel equations, 
 wherein the means for simulating the serial circuit includes
 means for simulating the serial circuit for a plurality of cycles as required to produce one output represented by the plurality of parallel equations. 
 
 
   
   
     16. The apparatus as recited in  claim 15 , wherein the means for storing one or more ASCII strings in each of the one or more data structures comprises:
 means for storing an ASCII string “XOR” for each addition operation in the serial circuit; and 
 means for storing an ASCII string “AND” for each multiplication operation in the serial circuit. 
 
   
   
     17. The apparatus as recited in  claim 15 , wherein the complex polynomial equation is a Bose-Chaudhuri-Hocquenghem (BCH) code utilized in forward error correction circuitry. 
   
   
     18. An apparatus for implementing a circuit representing a complex polynomial equation in an ASIC (Application Specific Integrated Circuit) comprising:
 means for producing one or more parallel equations in a hardware description language, 
 wherein the means for producing the one or more parallel equations comprises:
 means for implementing a serial circuit representing the complex polynomial equation in a software program, and 
 means for simulating the serial circuit to produce the one or more parallel equations; 
 
 means for merging the one or more parallel equations into a hardware description language implementation of a Galois Field circuit; 
 means for synthesizing the hardware description language description implementation into a gate level implementation; and 
 means for manufacturing the ASIC from the gate level implementation. 
 
   
   
     19. The apparatus as recited in  claim 18 , wherein the means for implementing the serial circuit comprises:
 means for storing a plurality of ASCII strings in each of a plurality of storage elements, wherein the plurality of ASCII strings represent a plurality of initial values of the serial circuit; and 
 means for storing one or more ASCII strings in each of one or more data structures wherein the one or more ASCII strings represent one or more mathematical operations in the serial circuit. 
 
   
   
     20. The apparatus as recited in  claim 19 , wherein the means for storing the one or more ASCII strings in each of the one or more data structures comprises:
 means for storing an ASCII string “XOR” for each addition operation in the serial circuit; and 
 means for storing an ASCII string “AND” for each multiplication operation in the serial circuit. 
 
   
   
     21. The apparatus as recited in  claim 18 , wherein the means for simulating the serial circuit to produce parallel equations comprises:
 means for executing the serial circuit for a plurality of cycles as required to produce one output represented by the plurality of parallel equations. 
 
   
   
     22. The apparatus as recited in  claim 18 , wherein the complex polynomial equation is a Bose-Chaudhuri-Hocquenghem (BCH) code utilized in forward error correction circuitry. 
   
   
     23. The apparatus as recited in  claim 18 , wherein the means for merging the one or more parallel equations into a hardware description language implementation of a Galois Field circuit comprises:
 means for removing initial register values from each of the parallel equations; and 
 means for adding a feedback value to each of the parallel equations. 
 
   
   
     24. The apparatus as recited in  claim 18 , further comprising:
 means for simulating the gate level implementation to verify accurate design implementation. 
 
   
   
     25. An apparatus for performing Galois field decoding comprising:
 a receive line section module for receiving and aligning a SONET signal; 
 a Forward Error Correction (FEC) decoder coupled to the receive line section module, the FEC decoder for decoding FEC check bits in the SONET signal, wherein
 the FEC decoder comprises a first circuit that implements one or more parallel equations, and 
 the one or more parallel equations are generated by simulating a serial circuit; and 
 
 a receive demultiplexer coupled to the FEC decoder, the receive demultiplexer for demultiplexing the SONET signal into a plurality of SONET datastreams. 
 
   
   
     26. The apparatus as recited in  claim 25 , wherein the FEC decoder comprises:
 a circuit representing a complex polynomial equation made by the method of:
 producing one or more parallel equations in a hardware description language; and 
 
 merging the one or more parallel equations into a hardware description language implementation of a Galois Field circuit. 
 
   
   
     27. The apparatus as recited in  claim 26 , wherein producing the one or more parallel equations comprises:
 implementing the serial circuit representing the complex polynomial equation in a software program; and 
 simulating the serial circuit to produce the one or more parallel equations. 
 
   
   
     28. The apparatus as recited in  claim 27 , wherein implementing the serial circuit comprises:
 storing a plurality of ASCII strings in each of a plurality of storage elements, wherein the plurality of ASCII strings represent a plurality of initial values of the serial circuit; and 
 storing one or more ASCII strings in each of one or more data structures wherein the one or more ASCII strings represent one or more mathematical operations in the serial circuit. 
 
   
   
     29. The apparatus as recited in  claim 28 , wherein storing the one or more ASCII strings in each of one or more data structures comprises:
 storing an ASCII string “XOR” for each addition operation the serial circuit; and 
 storing an ASCII string “AND” for each multiplication operation in the serial circuit. 
 
   
   
     30. The apparatus as recited in  claim 26 , the method further comprising:
 synthesizing the hardware description language description implementation into a gate level implementation; and 
 manufacturing the ASIC from the gate level implementation. 
 
   
   
     31. The apparatus as recited in  claim 27 , wherein simulating the serial circuit comprises:
 executing the serial circuit for a plurality of cycles as required to produce one output represented by the plurality of parallel equations. 
 
   
   
     32. The apparatus as recited in  claim 30 , the method further comprising:
 simulating the gate level implementation to verify accurate design implementation. 
 
   
   
     33. The apparatus as recited in  claim 26 , wherein the complex polynomial equation is a Bose-Chaudhuri-Hocquenghem (BCH) code. 
   
   
     34. The apparatus as recited in  claim 26 , wherein merging the one or more parallel equations into a hardware description language implementation of a Galois Field circuit comprises:
 removing initial register values from each of the parallel equations; and 
 adding a feedback value to each of the parallel equations. 
 
   
   
     35. An apparatus for performing Galois field encoding comprising:
 a transmit demultiplexer section module for receiving and aligning a plurality of SONET datastreams; 
 a Forward Error Correction (FEC) encoder coupled to the transmit demultiplexer section module, the FEC encoder for calculating and inserting FEC check bits into the plurality of SONET datastreams, wherein
 the FEC encoder comprises a first circuit that implements one or more parallel equations, and 
 the one or more parallel equations are generated by simulating a serial circuit; and 
 
 a transmit line section module coupled to the FEC encoder, the transmit line section module for multiplexing the SONET data streams into a SONET signal. 
 
   
   
     36. The apparatus as recited in  claim 35 , wherein the FEC encoder comprises:
 a circuit representing a complex polynomial equation made by the method of: 
 producing one or more parallel equations in a hardware description language; and 
 merging the one or more parallel equations into a hardware description language implementation of a Galois Field circuit. 
 
   
   
     37. The apparatus as recited in  claim 36 , wherein producing the one or more parallel equations comprises:
 implementing the serial circuit representing the complex polynomial equation in a software program; and 
 simulating the serial circuit to produce the one or more parallel equations. 
 
   
   
     38. The apparatus as recited in  claim 37 , wherein implementing the serial circuit comprises:
 storing a plurality of ASCII strings in each of a plurality of storage elements, wherein the plurality of ASCII strings represent a plurality of initial values of the serial circuit; and 
 storing one or more ASCII strings in each of one or more data structures wherein the one or more ASCII strings represent one or more mathematical operations in the serial circuit. 
 
   
   
     39. The apparatus as recited in  claim 38 , wherein storing the one or more ASCII strings in each of one or more data structures comprises:
 storing an ASCII string “XOR” for each addition operation the serial circuit; and 
 storing an ASCII string “AND” for each multiplication operation in the serial circuit. 
 
   
   
     40. The apparatus as recited in  claim 37 , wherein simulating the serial circuit comprises:
 executing the serial circuit for a plurality of cycles as required to produce one output represented by the plurality of parallel equations. 
 
   
   
     41. The apparatus as recited in  claim 36 , the method further comprising:
 synthesizing the hardware description language description implementation into a gate level implementation; and 
 manufacturing the ASIC from the gate level implementation. 
 
   
   
     42. The apparatus as recited in  claim 41 , the method further comprising:
 simulating the gate level implementation to verify accurate design implementation. 
 
   
   
     43. The apparatus as recited in  claim 36 , wherein the complex polynomial equation is a Bose-Chaudhuri-Hocquenghem (BCH) code. 
   
   
     44. The apparatus as recited in  claim 36 , wherein merging the one or more parallel equations into a hardware description language implementation of a Galois Field circuit comprises:
 removing initial register values from each of the parallel equations; and 
 adding a feedback value to each of the parallel equations.