Single chip power amplifier and envelope modulator

Abstract

RF polar modulation circuit has a self-compensated temperature stable envelope controller and self-compensated temperature stable power amplifier bias. The circuit has an adaptive current-to-voltage modulation interface with pre-distortion compensation capability. AM/PM distortion are compensated for envelope dependent power amplifier transistor biasing. Automatic compensation is provided for RF loads that are higher or lower than nominal loads. This Abstract is provided to comply with rules requiring an Abstract that allows a searcher or other reader to quickly ascertain subject matter of the technical disclosure. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72( b ).

1. A method of implementing a radio frequency polar modulation circuit having a self-compensated temperature-stable power amplifier and a self-compensated temperature-stable envelope controller on a single chip, the method comprising the steps of:
 providing an envelope modulation current to the polar modulation circuit to compensate for temperature offsets; 
 converting the envelope modulation current to an envelope modulation voltage; 
 providing the envelope modulation voltage to the envelope controller; 
 modulating a power supply of the power amplifier using the envelope controller; and 
 limiting a maximum output power of the power amplifier to less than or equal to a predetermined value for a given envelope modulation current. 
 
   
   
     2. The method according to  claim 1 , wherein the step of limiting a maximum output power of the power amplifier is performed using a biasing network connected to the power amplifier, the maximum output power of the power amplifier is set by a biasing current provided to the biasing network and an output impedance of the biasing network. 
   
   
     3. The method according to  claim 2 , wherein the power amplifier comprises bipolar junction transistors, the biasing network connected to the power amplifier by a resistive element connected to the base terminals of the bipolar junction transistors. 
   
   
     4. The method according to  claim 2 , wherein the power amplifier comprises field effect transistors, the biasing network connected to the power amplifier by a resistive element connected to the gate terminals of the field effect transistors. 
   
   
     5. The method according to  claim 1  wherein the step of converting the envelope modulation current to an envelope modulation voltage comprises inputting the envelope modulation current into a current mirror. 
   
   
     6. The method according to  claim 5 , further comprising adjusting the envelope modulation voltage provided to the input of the envelope controller to compensate for distortion due to power amplifier performance by connecting a resistive element between the supply voltage terminals of the current mirror. 
   
   
     7. The method according to  claim 6 , wherein the resistive element is selected so as to minimize a voltage drop between a supply voltage of the current mirror and the input of the envelope controller. 
   
   
     8. The method according to  claim 7 , further comprising adjusting the envelope modulation voltage of the envelope controller to compensate for distortion due to load variation by adaptively changing a value of the resistive element connected between the supply voltage terminals of the current mirror based on the envelope modulation current and an output signal amplitude of the power amplifier. 
   
   
     9. The method according to  claim 5 , wherein the step of limiting a maximum output power of the power amplifier comprises detecting when an output signal amplitude of the power amplifier has exceeded a threshold voltage and adaptively changing a value of one or more preselected components of the polar modulation circuit until the output signal amplitude no longer exceeds the threshold voltage. 
   
   
     10. The method according to  claim 9 , wherein the one or more preselected components include a resistive element in the current mirror connecting the current mirror to ground. 
   
   
     11. The method according to  claim 5 , further comprising compensating for an offset in the envelope modulation current by providing a transistor in the current mirror that has the same saturation voltage as the power amplifier. 
   
   
     12. The method according to  claim 1 , further comprising biasing the power amplifier by providing a biasing current having a value that is dependent on an output signal amplitude of the envelope controller and using a biasing network to convert the biasing current to a biasing voltage to compensate for thermal offset. 
   
   
     13. The method according to  claim 1 , further comprising: providing a separate supply voltage to each transistor stage of the power amplifier; and wherein each separate supply voltage has been optimized for its respective transistor stage. 
   
   
     14. The method according to  claim 13 , wherein two or more transistor stages of the power amplifier share the same supply voltage. 
   
   
     15. The method according to  claim 1 , further comprising protecting a regulator transistor of the envelope controller when its supply voltage exceeds a predetermined amount by providing a protective transistor between the regulator transistor and the power amplifier, the protective transistor biased by a diode network and a current source such that the envelope controller consumes essentially zero current when in an off state to allow the polar modulation circuit to be implemented using low voltage transistors. 
   
   
     16. A single-chip radio frequency polar modulation circuit having a self-compensated temperature-stable envelope controller and a self-compensated temperature-stable power amplifier, the circuit comprising: a current-to-voltage interface configured to receive an envelope modulation current, convert the envelope modulation current to an envelope modulation voltage, and provide the envelope modulation voltage to an input of the envelope controller, the current-to-voltage interface being substantially temperature insensitive; and means for limiting a maximum output power of the power amplifier to less than or equal to a predetermined value for a given envelope modulation current. 
   
   
     17. The polar modulation circuit according to  claim 16 , wherein the means for limiting a maximum output power of the power amplifier includes a biasing network connected to the power amplifier, the maximum output power of the power amplifier is set by a biasing current provided to the biasing network and an output impedance of the biasing network. 
   
   
     18. The polar modulation circuit according to  claim 17 , wherein the power amplifier comprises bipolar junction transistors, the biasing network connected to the power amplifier by a resistive element connected to the base terminals of the bipolar junction transistors. 
   
   
     19. The polar modulation circuit according to  claim 17 , wherein the power amplifier comprises field effect transistors, the biasing network connected to the power amplifier by a resistive element connected to the gate terminals of the field effect transistors. 
   
   
     20. The polar modulation circuit according to  claim 16 , wherein the current-to-voltage interface includes a current mirror and the envelope modulation current is converted to an envelope modulation voltage by inputting the envelope modulation current into the current mirror. 
   
   
     21. The polar modulation circuit according to  claim 20 , wherein the current-to-voltage interface further includes a resistive element connected between the supply voltage terminals of the current mirror, the resistive element configured to adjust the envelope modulation voltage to compensate for distortion due to power amplifier performance. 
   
   
     22. The polar modulation circuit according to  claim 21 , wherein the resistive element is selected so as to minimize a voltage drop between a supply voltage of the current mirror and the input of the envelope controller. 
   
   
     23. The polar modulation circuit according to  claim 22 , further comprising: an envelope detector for measuring an output signal amplitude of the power amplifier; and a predictor for adaptively changing a value of the resistive element connected between the supply voltage terminals of the current mirror based on the envelope modulation current and the output signal amplitude of the power amplifier to compensate for distortion due to load variation. 
   
   
     24. The polar modulation circuit according to  claim 23 . wherein the means for limiting a maximum output power of the power amplifier comprises: an envelope limiter for detecting when the output signal amplitude of the power amplifier has exceeded a threshold voltage; and a controller for adaptively changing a value of one or more preselected components of the polar modulation circuit until the output signal amplitude no longer exceeds the threshold voltage. 
   
   
     25. The polar modulation circuit according to  claim 24 , wherein the one or more preselected components include a resistive element in the current mirror connecting the current mirror to ground. 
   
   
     26. The polar modulation circuit according to  claim 20 , further comprising a transistor in the current mirror connecting the current mirror to ground that has the same saturation voltage as the power amplifier for compensating an offset in the envelope modulation current. 
   
   
     27. The polar modulation circuit according to  claim 16 , further comprising a biasing network configured to convert a biasing current having a value that is dependent on an output signal amplitude of the envelope controller to a biasing voltage and provide the biasing voltage to the power amplifier to compensate for thermal offset. 
   
   
     28. The polar modulation circuit according to  claim 16 , further comprising a separate supply voltage providing a biasing voltage to each transistor stage of the power amplifier; and wherein each separate supply voltage has been optimized for its respective transistor stage. 
   
   
     29. The polar modulation circuit according to  claim 28 , wherein two or more transistor stages of the power amplifier share the same supply voltage. 
   
   
     30. The polar modulation circuit according to  claim 16 , further comprising a protective transistor connected between a regulator transistor of the envelope controller and the power amplifier for protecting the regulator transistor when a supply voltage thereof exceeds a predetermined amount, the protective transistor biased by a diode network and a current source such that the envelope controller consumes essentially zero current when in an off state to allow the polar modulation circuit to be implemented using low voltage transistors.