Receiving circuit

Abstract

A receiving circuit comprises an A/D converter which converts a receive signal to a digital signal having a first data format at a sampling rate corresponding to twice the spreading bandwidth of the receive signal, an analog front-end interface which converts the first data format of the digital signal to a second data format, a searcher which detects a phase of the digital signal having the second data format to perform a synchronization capture and outputs a timing signal, an interpolation filter which samples the digital signal having the second data format at a sampling rate different from the sampling rate of the A/D converter, a rake receiver which detects the synchronism of a signal outputted from the interpolation filter based on the timing signal and a demodulator which demodulates a signal outputted from the rake receiver.

1. A receiving circuit, comprising:
 an A/D converter which converts a receive signal to a digital signal having a first data format at a sampling rate corresponding to twice the spreading bandwidth of the receive signal; 
 an analog front-end interface which converts said first data format of said digital signal to a second data format; 
 a searcher which detects a phase of said digital signal having said second data format to perform a synchronization capture and outputs a timing signal; 
 an interpolation filter which samples said digital signal having said second data format at a sampling rate different from said sampling rate of said A/D converter; 
 a rake receiver which detects the synchronism of a signal outputted from said interpolation filter, based on said timing signal; and 
 a demodulator which demodulates a signal outputted from said rake receiver. 
 
   
   
     2. The receiving circuit according to  claim 1 , further comprising a low-pass filter which cuts a high-frequency component of a receive signal and outputs a filtered receive signal to the A/D converter. 
   
   
     3. The receiving circuit according to  claim 1 , further comprising a DC offset adjust which compensates for a DC offset of the digital signal having the second data format and outputs a compensated digital signal having the second data format. 
   
   
     4. The receiving circuit according to  claim 3 , further comprising a receive filter which extracts only a receiving band from the digital signal output by the DC offset adjust. 
   
   
     5. The receiving circuit according  claim 1 , wherein the rake receiver comprises:
 a plurality of fingers, each finger demodulating the signal output by the interpolation filter according to the timing signal; and 
 a combiner which combines demodulated signals output from each finger. 
 
   
   
     6. The receiving circuit according to  claim 5 , wherein each finger comprises:
 a decimator which latches the signal output from the interpolation filter based on a decimation timing information signal and outputs a latched signal; 
 a correlator early which performs a sum-of-products operation using a spread code whose phase is slightly advanced as compared with the latched signal; 
 a correlator late which performs a sum-of-products operation using a spread code whose phase is slightly delayed as compared with the latched signal; 
 a DLL which generates the decimation timing information signal based on the signals output from the correlator early and the correlator late; and 
 a data demodulator which demodulates the latched signal.