High performance diode-implanted voltage-controlled poly resistors for mixed-signal and RF applications

Abstract

A p-type polysilicon resistor formed in the inter-level dielectric layer contains an implanted diode. A positive voltage applied to the diode modulates the depletion region of the diode and changes the absolute resistance of the p-type polysilicon resistor. This modulation occurs not only horizontally, but also vertically. The fact that the tunable resistor is a p-type polysilicon resistor means that this structure can easily be integrated into the process since polysilicon is used as a gate material for basic CMOS processing.

1. A resistor formed on a silicon chip, said resistor comprising:
 a region of polysilican that is doped with a p-type dopant and is electrically isolated from a substrate by a dielectric, said region of polysilicon having first and second contact regions on opposite ends of said region, said first and second contact regions being doped with a p-type dopant; and 
 first and second diodes formed within said region of polysilicon and connected to be reversed biased such that a voltage applied to said first and said second diodes creates first and second depletion regions that lower the resistance value of said resistor. 
 
   
   
     2. The resistor of  claim 1 , wherein said region of polysilicon is isolated from said substrate by being located on a trench filled with an oxide. 
   
   
     3. A resistor formed on a silicon chip, said resistor comprising:
 a first region of polysilicon that is doped with a p-type dopant and is electrically isolated from a substrate by a dielectric; 
 second and third regions contained within said first region at opposite ends of said first region, said second and third regions being doped with a p-type dopant at a level that makes them effective as contact region; 
 fourth and fifth regions contained within said first region, said fourth and fifth regions being doped with an n-type dopant at a level that makes them effective as contact regions, said fourth and fifth regions partially occluding a path between said second and third regions. 
 
   
   
     4. The resistor of  claim 3 , further comprising portions of a layer of silicide overlying said second, third, fourth, and fifth regions, but not portions of said first regions that are outside said second, third, fourth and fifth regions. 
   
   
     5. The resistor of  claim 4 , further comprising metal contacts overlying said portions of said layer of silicide. 
   
   
     6. The resistor of  claim 3 , wherein said fourth and said fifth regions are connected as reverse-biased diodes. 
   
   
     7. The resistor of  claim 3 , wherein said second and third regions are connected to pass a current through said first region. 
   
   
     8. The resistor of  claim 3 , wherein said second and third regions are connected to pass a current through said first region and said fourth and said fifth regions are connected as reverse-biased diodes;
 whereby applying a positive voltage to said fourth and fifth regions changes the value of a current passing between said second and third regions. 
 
   
   
     9. The resistor of  claim 1 , wherein said first end second depletion regions partially occlude a path between said first and second contact regions. 
   
   
     10. A semiconductor chip, said semiconductor chip comprising:
 a first region of substrate containing digital logic circuitry; 
 a second region of substrate containing analog circuitry; and 
 a resistor formed on a trench of oxide and electrically isolated from said substrate, said resistor containing 
 a third region of polysilicon that is doped with a p-type dopant; 
 fourth and filth regions contained within said third region at opposite ends of said third region, said fourth and fifth regions being doped with a p-type dopant at a level that makes them effective as contact regions; 
 sixth and seventh regions contained within said third region, said sixth and seventh regions being doped with an n-type dopant at a level that makes them effective as contact regions, said sixth and seventh regions partially occluding a path between said fourth and fifth regions. 
 
   
   
     11. The semiconductor chip of  claim 10 , further comprising portions of a layer of silicide overlying said fourth, fifth, sixth, and seventh regions, but not portions of said first regions that are outside said second, third, fourth and fifth regions. 
   
   
     12. The semiconductor chip of  claim 11 , further comprising metal contacts overlying said portions of said layer of silicide. 
   
   
     13. The semiconductor chip of  claim 10 , wherein said sixth and said seventh regions are connected as reverse-biased diodes. 
   
   
     14. The semiconductor chip of  claim 10 , wherein said fourth and fifth regions are connected to pass a current through said third region. 
   
   
     15. The semiconductor chip of  claim 10 , wherein said fourth and fifth regions are connected to pass a current through said third region and said six and seventh regions are connected as reverse-biased diodes;
 whereby applying a positive voltage to said sixth and seventh regions decreases the current passing between said fourth and fifth regions.