Sharing operational amplifier between two stages of pipelined ADC and/or two channels of signal processing circuitry

Abstract

A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital converter and/or two channels of signal processing circuitry, before the amplifier configuration of the stages/channels is switched. The discharging act occurs when a short reset pulse is generated between two clock phases. The short reset pulse is applied to a switch connected to the operational amplifier input. When the reset pulse closes the switch, a discharge path is created and any parasitic capacitance at the operational amplifier input is discharged through the path. The discharging of the parasitic capacitance substantially mitigates the memory effect and the problems associated with the memory effect.

1. A method of operating a pipelined analog-to-digital converter comprising first and second stages sharing an amplifier, said method comprising the acts of:
 performing a first operation in the first stage in accordance with a first clock signal; 
 performing a second operation in the second stage in accordance with the first clock signal; and 
 performing a first discharge operation at the amplifier in accordance with a first reset pulse. 
 
   
   
     2. The method of  claim 1 , further comprising the acts of:
 performing the second operation in the first stage in accordance with a second clock signal; and 
 performing the first operation in the second stage in accordance with the second clock signal. 
 
   
   
     3. The method of  claim 2  further comprising the act of performing a second discharge operation at the amplifier in accordance with a second reset pulse. 
   
   
     4. The method of  claim 3 , wherein the first reset pulse is generated after the first clock signal transitions from a first state to a second state and the second reset pulse is generated after the second clock signal transitions from the first state to the second state. 
   
   
     5. The method of  claim 1 , wherein the first reset pulse is generated after the first clock signal transitions from a first state to a second state. 
   
   
     6. The method of  claim 1 , wherein the first operation is a sampling operation and the second operation is an amplifying operation. 
   
   
     7. The method of  claim 1 , wherein the first operation is an amplifying operation and the second operation is a sampling operation. 
   
   
     8. The method of  claim 1 , wherein the discharge operation comprises the act of connecting an input of the amplifier to a ground potential. 
   
   
     9. The method of  claim 1 , wherein the discharge operation comprises the act of creating a path to discharge parasitic capacitance from an input of the amplifier to a discharge area. 
   
   
     10. A method of operating signal processing circuitry comprising two channels sharing an amplifier, said method comprising the acts of:
 performing a first operation in the first channel in accordance with a first clock signal; 
 performing a second operation in the second channel in accordance with the first clock signal; and 
 performing a first discharge operation at the amplifier in accordance with a first reset pulse. 
 
   
   
     11. The method of  claim 10 , further comprising the acts of:
 performing the second operation in the first channel in accordance with a second clock signal; and 
 performing the first operation in the second channel in accordance with the second clock signal. 
 
   
   
     12. The method of  claim 11  further comprising the act of performing a second discharge operation at the amplifier in accordance with a second reset pulse. 
   
   
     13. A pipelined analog-to-digital converter, comprising:
 first and second pipeline stages, said pipeline stages sharing an amplifier; and 
 means for generating non-overlapping first and second clock signals and a plurality of reset pulses, said means applying the first and second clock signals and the reset pulses to the stages, 
 wherein said first clock signal causes said first stage to perform a first operation and said second stage to perform a second operation, and said reset pulses cause a discharge operation to occur at an input of said amplifier. 
 
   
   
     14. The converter of  claim 13 , wherein said discharge operation forms a parasitic capacitance discharge path from the input of the amplifier to a discharge area. 
   
   
     15. The converter of  claim 13 , wherein said second clock signal causes said first stage to perform the second operation and said second stage to perform the first operation. 
   
   
     16. The converter of  claim 13 , wherein the first operation is a sampling operation and the second operation is an amplifying operation. 
   
   
     17. The converter of  claim 13 , wherein the first operation is an amplifying operation and the second operation is a sampling operation. 
   
   
     18. The converter of  claim 13 , further comprising a switch coupled between a ground potential and the input the amplifier, wherein the pulses connect the input of the amplifier to the ground potential by closing said switch. 
   
   
     19. The converter of  claim 13 , wherein the reset pulses are generated after the first clock signal transitions from a first state to a second state and after the second clock signal transitions from the first state to the second state. 
   
   
     20. The converter of  claim 13  wherein said generating means comprises a clock generator. 
   
   
     21. The converter of  claim 13 , further comprising:
 third and fourth pipeline stages, said third and fourth pipeline stages sharing a second amplifier and being connected to receive the first and second clock signals and reset pulses, 
 said first clock signal causing said third stage to perform the first operation and said fourth stage to perform the second operation, and said reset pulses cause the discharge operation to occur at an input of said second amplifier. 
 
   
   
     22. A pipelined analog-to-digital converter, comprising:
 a plurality of pairs of pipeline stages, each pair of stages sharing an associated amplifier; and 
 means for generating non-overlapping first and second clock signals and a plurality of reset pulses, said means applying the first and second clock signals and the reset pulses to each pair of stages, 
 wherein said first clock signal causes one stage of each pair to perform a first operation and a second stage of each pair to perform a second operation, and said reset pulses cause a discharge operation to occur at an input of the amplifier within each pair. 
 
   
   
     23. The converter of  claim 22 , wherein said discharge operation forms a parasitic capacitance discharge path from the input of the amplifiers to respective discharge areas. 
   
   
     24. The converter of  claim 22 , wherein the first operation is a sampling operation and the second operation is an amplifying operation. 
   
   
     25. The converter of  claim 22 , wherein the first operation is an amplifying operation and the second operation is a sampling operation. 
   
   
     26. The converter of  claim 22 , wherein each pair further comprises a switch coupled between a ground potential and the input the associated amplifier, wherein the pulses connect the input of the amplifiers to the ground potential by closing said switch. 
   
   
     27. The converter of  claim 22 , wherein the reset pulses are generated after the first clock signal transitions from a first state to a second state and after the second clock signal transitions from the first state to the second state. 
   
   
     28. An imager comprising:
 a pixel array; 
 sample and hold circuitry coupled to receive analog signals from pixels within the array; 
 an amplification circuit for amplifying the analog signals; and 
 a pipelined analog-to-digital converter connected to receive and convert the amplified analog signals to digital signals, said converter comprising:
 first and second pipeline stages, said pipeline stages sharing an amplifier, and means for generating non-overlapping first and second clock signals and a plurality of reset pulses, said means applying the first and second clock signals and the reset pulses to the stages, 
 wherein said first clock signal causes said first stage to perform a first operation and said second stage to perform a second operation, and said reset pulses cause a discharge operation to occur at an input of said amplifier. 
 
 
   
   
     29. The imager of  claim 28 , wherein said discharge operation forms a parasitic capacitance discharge path from the input of the amplifier to a discharge area. 
   
   
     30. The imager of  claim 28 , wherein said second clock signal causes said first stage to perform the second operation and said second stage to perform the first operation. 
   
   
     31. The imager of  claim 28 , wherein the first operation is a sampling operation and the second operation is an amplifying operation. 
   
   
     32. The imager of  claim 28 , wherein the first operation is an amplifying operation and the second operation is a sampling operation. 
   
   
     33. The imager of  claim 28 , wherein said analog-to-digital converter further comprises a switch coupled between a ground potential and the input the amplifier, wherein the pulses connect the input of the amplifier to the ground potential by closing said switch. 
   
   
     34. The imager of  claim 28 , wherein the reset pulses are generated after the first clock signal transitions from a first state to a second state and after the second clock signal transitions from the first state to the second state. 
   
   
     35. The imager of  claim 28 , wherein said analog-to-digital converter further comprises:
 third and fourth pipeline stages, said third and fourth pipeline stages sharing a second amplifier and being connected to receive the first and second clock signals and reset pulses, 
 said first clock signal causing said third stage to perform the first operation and said fourth stage to perform the second operation, and said reset pulses cause the discharge operation to occur at an input of said second amplifier. 
 
   
   
     36. An imager comprising:
 a pixel array; 
 sample and hold circuitry coupled to receive analog signals from pixels within the array; 
 an amplification circuit for amplifying the analog signals; and 
 a pipelined analog-to-digital converter connected to receive and convert the amplified analog signals to digital signals, said converter comprising:
 a plurality of pairs of pipeline stages, each pair of stages sharing an associated amplifier, and means for generating non-overlapping first and second clock signals and a plurality of reset pulses, said means applying the first and second clock signals and the reset pulses to each pair of stages, 
 wherein said first clock signal causes one stage of each pair to perform a first operation and a second stage of each pair to perform a second operation, and said reset pulses cause a discharge operation to occur at an input of the amplifier within each pair. 
 
 
   
   
     37. The imager of  claim 36 , wherein said discharge operation forms a parasitic capacitance discharge path from the input of the amplifiers to respective discharge areas. 
   
   
     38. The imager of  claim 36 , wherein the first operation is a sampling operation and the second operation is an amplifying operation. 
   
   
     39. The imager of  claim 36 , wherein the first operation is an amplifying operation and the second operation is a sampling operation. 
   
   
     40. The imager of  claim 36 , wherein each pair further comprises a switch coupled between a ground potential and the input the associated amplifier, wherein the pulses connect the input of the amplifiers to the ground potential by closing said switch. 
   
   
     41. The imager of  claim 36 , wherein the reset pulses are generated after the first clock signal transitions from a first state to a second state and after the second clock signal transitions from the first state to the second state. 
   
   
     42. An imager comprising:
 a pixel array; 
 a first signal processing channel coupled to receive first analog signals from pixels within the array; 
 a second signal processing channel coupled to receive second analog signals from pixels within the array; 
 at least one amplifier shared by the first and second channels; 
 means for generating non-overlapping first and second clock signals and a plurality of reset pulses, said means applying the first and second clock signals and the reset pulses to each channel and the at least one amplifier, 
 wherein said first clock signal causes the first channel to perform a first operation and the second channel to perform a second operation, and said reset pulses cause a discharge operation to occur at the amplifier. 
 
   
   
     43. The imager of  claim 42 , wherein the first operation is a sampling operation and the second operation is an amplifying operation. 
   
   
     44. The imager of  claim 42 , wherein the first operation is an amplifying operation and the second operation is a sampling operation. 
   
   
     45. The imager of  claim 42 , wherein the reset pulses are generated after the first clock signal transitions from a first state to a second state and after the second clock signal transitions from the first state to the second state.