Method and apparatus for extending the bandwidth of a Class D amplifier circuit

Abstract

Class D amplifiers are used for their high efficiency, but they have some undesirable characteristics that limit their useable bandwidth, one of these being the residual switching frequency ripple. Embodiments of the present invention comprise methods and apparatuses for reducing the switching frequency ripple using a technique known herein as ripple steering. The zero ripple class D amplifier is used in a hybrid system comprising a linear amplifier. The hybrid Class D amplifier is modified for extended bandwidth and lowered distortion by the addition of a linear current source feeding output capacitor. The low frequency bandwidth limit on the linear current source is matched to the high frequency bandwidth limit on the Class D current source, resulting in a composite linear/switching current source with bandwidth extended to the high frequency bandwidth limit of the linear current source.

1. A method for extending the bandwidth of a class D amplifier system comprising:
 obtaining a class D amplifier circuit with zero switching ripple, said class D amplifier circuit having a first output capacitor; 
 generating a first current source for charging said output capacitor using a current mode control loop around said class D amplifier; 
 generating a second current source for additionally charging said output capacitor, said second current source extending bandwidth of said first current source. 
 
   
   
     2. The method of  claim 1 , wherein said class D amplifier circuit with zero switching ripple comprises:
 a first set of switches coupled together to form a first switching node; 
 a first coupled inductor circuit having a first primary winding and a first secondary winding, wherein one end of said first primary winding and one end of said first secondary winding are coupled together and to said first switching node; 
 said first output capacitor coupled to said first primary winding and to ground; and 
 an auxiliary output circuit coupled to said first secondary winding. 
 
   
   
     3. The method of  claim 1 , wherein said second current source is a linear amplifier. 
   
   
     4. The method of  claim 2 , wherein said first current source for charging said output capacitor comprises output of said first primary winding. 
   
   
     5. The method of  claim 2 , wherein said second current source is a linear amplifier. 
   
   
     6. The method of  claim 1 , wherein said class D amplifier circuit with zero switching ripple comprises:
 a first set of switches coupled together to form a first switching node; 
 a first core comprising a first coupled inductor circuit having a first primary winding and a first secondary winding, wherein a first end of said first primary winding is coupled to said first switching node, a second end of said first secondary winding is coupled to a second end of said first primary winding, said first secondary winding is back-wound from said second end to a first end of said first secondary winding in said first core; 
 a first capacitor coupled to said second end of said first primary winding and to ground; and 
 an auxiliary output circuit coupled to said first end of said first secondary winding. 
 
   
   
     7. The method of  claim 6 , wherein said first current source for charging said output capacitor comprises output of said first primary winding. 
   
   
     8. The method of  claim 6 , wherein said second current source is a linear amplifier. 
   
   
     9. The method of  claim 1 , wherein said class D amplifier circuit with zero switching ripple comprises:
 a first set of switches coupled together to form a first switching node; 
 a first inductor circuit having a first primary winding from a first end to a second end and a tap at a first intermediate point therein, wherein said first end of said first primary winding is coupled to said first switching node; 
 a first capacitor coupled to said second end of said first primary winding and to ground; and 
 an auxiliary output circuit coupled to said tap at said first intermediate point in said primary winding. 
 
   
   
     10. The method of  claim 9 , wherein said first current source for charging said output capacitor comprises output of said first primary winding. 
   
   
     11. The method of  claim 9 , wherein said second current source is a linear amplifier. 
   
   
     12. A class D amplifier apparatus with extended bandwidth comprising:
 a class D amplifier circuit with zero switching ripple, said class D amplifier circuit having a first output capacitor; 
 a first current source for charging said output capacitor having a current mode control loop around said class D amplifier; 
 a second current source for additionally charging said output capacitor, said second current source extending bandwidth of said first current source. 
 
   
   
     13. The class D amplifier apparatus of  claim 12 , wherein said class D amplifier circuit with zero switching ripple comprises:
 a first set of switches coupled together to form a first switching node; 
 a first coupled inductor circuit having a first primary winding and a first secondary winding, wherein one end of said first primary winding and one end of said first secondary winding are coupled together and to said first switching node; 
 said first output capacitor coupled to said first primary winding and to ground; and 
 an auxiliary output circuit coupled to said first secondary winding. 
 
   
   
     14. The class D amplifier apparatus of  claim 12 , wherein said second current source is a linear amplifier. 
   
   
     15. The class D amplifier apparatus of  claim 13 , wherein said first current source for charging said output capacitor comprises output of said first primary winding. 
   
   
     16. The class D amplifier apparatus of  claim 13 , wherein said second current source is a linear amplifier. 
   
   
     17. The class D amplifier apparatus of  claim 12 , wherein said class D amplifier circuit with zero switching ripple comprises:
 a first set of switches coupled together to form a first switching node; 
 a first core comprising a first coupled inductor circuit having a first primary winding and a first secondary winding, wherein a first end of said first primary winding is coupled to said first switching node, a second end of said first secondary winding is coupled to a second end of said first primary winding, said first secondary winding is back-wound from said second end to a first end of said first secondary winding in said first core; 
 a first capacitor coupled to said second end of said first primary winding and to ground; and 
 an auxiliary output circuit coupled to said first end of said first secondary winding. 
 
   
   
     18. The class D amplifier apparatus of  claim 17 , wherein said first current source for charging said output capacitor comprises output of said first primary winding. 
   
   
     19. The class D amplifier apparatus of  claim 17 , wherein said second current source is a linear amplifier. 
   
   
     20. The class D amplifier apparatus of  claim 12 , wherein said class D amplifier circuit with zero switching ripple comprises:
 a first set of switches coupled together to form a first switching node; 
 a first inductor circuit having a first primary winding from a first end to a second end and a tap at a first intermediate point therein, wherein said first end of said first primary winding is coupled to said first switching node; 
 a first capacitor coupled to said second end of said first primary winding and to ground; and 
 an auxiliary output circuit coupled to said tap at said first intermediate point in said primary winding. 
 
   
   
     21. The class D amplifier apparatus of  claim 20 , wherein said first current source for charging said output capacitor comprises output of said first primary winding. 
   
   
     22. The class D amplifier apparatus of  claim 20 , wherein said second current source is a linear amplifier.