US7167117B2ExpiredUtilityPatentIndex 72
Test circuit for digital to analog converter in liquid crystal display driver
Est. expiryAug 5, 2024(expired)· nominal 20-yr term from priority
Inventors:CHOE SEONG-MIN
H03M 1/66H03M 1/1071G01R 31/28
72
PatentIndex Score
7
Cited by
16
References
8
Claims
Abstract
A test device for testing a digital to analog converter includes a gamma reference unit for generating a plurality of analog signals different from each other; a temporary storing unit for generating a plurality of digital signals different from each other; a decoder for selecting one of the plurality of analog signals or one of the plurality of digital signals in response to a digital code signal; and a switching unit for controlling a connection between the decoder and the gamma reference unit and between the decoder and the temporary storing unit according to an operation mode.
Claims
exact text as granted — not AI-modified1. A test device for testing a digital to analog converter, comprising:
a gamma reference unit for generating a plurality of analog signals different from each other;
a temporary storing unit for generating a plurality of digital signals different from each other;
a decoder for selecting one of the plurality of analog signals or one of the plurality of digital signals in response to a digital code signal; and
a switching unit for controlling a connection between the decoder and the gamma reference unit and between the decoder and the temporary storing unit according to an operation mode.
2. The test device as recited in claim 1 , wherein, at a normal mode, the decoder is connected to the gamma reference unit and is disconnected-from the temporary storing unit and, at a test mode, the decoder is disconnected from the gamma reference unit and is connected to the temporary storing unit.
3. The test device as recited in claim 2 , wherein it is determined whether the digital to analog converter is defective by measuring a voltage level of an output of an analog amplifier, wherein the analog amplifier receives an output of the decoder.
4. The test device as recited in claim 1 , wherein the temporary storing unit is a shift register.
5. The test device as recited in claim 1 , wherein the temporary storing unit is a register.
6. The test device as recited in claim 1 , wherein the temporary storing unit is a latch.
7. The test device as recited in claim 1 , wherein the temporary storing unit is a static random access memory (SRAM).
8. The test device as recited in claim 1 , wherein the gamma reference unit includes a series of resistors.Cited by (0)
No later patents cite this yet.
References (0)
No backward citations on record.