Self-calibration circuit for capacitance mismatch

Abstract

A self-calibration circuit for capacitance mismatch is provided. The circuit comprises a sample-and-hold (S/H) circuit, a comparator, and a switch control circuit. The S/H circuit comprises a compensation capacitor array, a target capacitor, and a reference capacitor. The S/H circuit provides an output voltage, wherein the output voltage is an operation result based on the capacitance of the target capacitor and the reference capacitor, and the equivalent capacitance of the compensation capacitor array. The comparator provides a comparison signal according to whether the output voltage of the S/H circuit is positive or negative. The switch control circuit controls the equivalent capacitance of the array according to the comparison signal such that the result of the target capacitance added to the equivalent capacitance of the array gradually approximates the reference capacitance with each cycle of a clock signal.

1. A self-calibration circuit for capacitance mismatch, comprising:
 a sample-and-hold (S/H) circuit, comprising:
 a compensation capacitor array; 
 a target capacitor; 
 a reference capacitor; 
 
 a comparator; and 
 a switch control circuit; wherein 
 the S/H circuit provides an output voltage, the output voltage is an operation result based on the capacitance of the target capacitor, of the reference capacitor, and the equivalent capacitance of the compensation capacitor array; 
 the comparator provides a comparison signal according to whether the output voltage of the S/H circuit is positive or negative; 
 the switch control circuit provides a compensation control signal to the compensation capacitor array to control the equivalent capacitance of the compensation capacitor array, and adjusts the compensation control signal according to the comparison signal for each cycle of a clock signal, such that the result of the target capacitance added to the equivalent capacitance of the compensation capacitor array gradually approximates the reference capacitance with each cycle of the clock signal. 
 
   
   
     2. The self-calibration circuit for capacitance mismatch as claimed in  claim 1 , wherein the output voltage of the S/H circuit is directly proportional to the result of adding the target capacitance to the equivalent capacitance of the compensation capacitor array and then subtracting the reference capacitance. 
   
   
     3. The self-calibration circuit for capacitance mismatch as claimed in  claim 2 , wherein the compensation capacitor array comprises:
 a plurality of compensation capacitors, each of the compensation capacitors being coupled to the output of the S/H circuit; and 
 a plurality of compensation switches, each of the compensation switches being coupled between one of the compensation capacitors and a first connection point, and turned on or turned off according to one bit in the compensation control signal; furthermore, 
 the target capacitor is coupled between the output of the S/H circuit and the first connection point; 
 the reference capacitor is coupled between the output of the S/H circuit and a second connection point. 
 
   
   
     4. The self-calibration circuit for capacitance mismatch as claimed in  claim 3 , wherein the switch control circuit generates a switch control signal according to a calibration activating signal, and the S/H circuit further comprises a first switch; if the switch control signal is at a first state, the first switch connects a reference voltage and the second connection point, and if the switch control signal is at a second state, the first switch connects the reference voltage and the first connection point. 
   
   
     5. The self-calibration circuit for capacitance mismatch as claimed in  claim 3 , wherein the predetermined value for the manufacturing process of the target capacitor is equal to the predetermined value for the manufacturing process of the reference capacitor multiplied by (1-DELTA), where DELTA is the standard capacitance deviation of the manufacturing process. 
   
   
     6. The self-calibration circuit for capacitance mismatch as claimed in  claim 3 , further, in the compensation capacitors, the predetermined value of the x th  compensation capacitor is larger than the predetermined value of the (x+1) th  compensation capacitor, where x is a positive integer. 
   
   
     7. The self-calibration circuit for capacitance mismatch as claimed in  claim 6 , further, in the compensation capacitors, the predetermined value of the x th  compensation capacitor is equal to the predetermined value of the (x+1) th  compensation capacitor multiplied by 2, where x is a positive integer. 
   
   
     8. The self-calibration circuit for capacitance mismatch as claimed in  claim 3 , further, in the compensation capacitors, the predetermined value of the first compensation capacitor is equal to the predetermined value of the target capacitor divided by 2 m , m<log 2 (1/DELTA)−1, where DELTA is the standard capacitance deviation of the manufacturing process. 
   
   
     9. The self-calibration circuit for capacitance mismatch as claimed in  claim 3 , further, among the compensation capacitors, the minimum predetermined value of a compensation capacitor is determined according to the smallest size allowable by the capacitor layout in the manufacturing process. 
   
   
     10. The self-calibration circuit for capacitance mismatch as claimed in  claim 3 , wherein the reference capacitor is formed by a plurality of capacitors connected in parallel. 
   
   
     11. The self-calibration circuit for capacitance mismatch as claimed in  claim 1 , wherein the comparator has an inverting input coupled to the output of the S/H circuit, and a non-inverting input being grounded, and an output being coupled to the switch control circuit. 
   
   
     12. The self-calibration circuit for capacitance mismatch as claimed in  claim 11 , wherein if the output voltage of the S/H circuit is positive, the comparison signal is at a second state; otherwise the comparison signal is at a first state. 
   
   
     13. The self-calibration circuit for capacitance mismatch as claimed in  claim 11 , further comprising a second switch, wherein the second switch is coupled between the non-inverting input and the inverting input of the comparator, and is turned on or turned off according to a switch control signal generated by the switch control circuit according to a calibration activating signal. 
   
   
     14. The self-calibration circuit for capacitance mismatch as claimed in  claim 1 , wherein the switch control circuit comprises:
 a shift register, providing a shift signal; in the x th  cycle of the clock signal, the x th  bit of the shift signal is at a first state, and the other bits are at a second state, where x is a positive integer; 
 a latch circuit, providing a latch signal, and latching the comparison signal as the x th  bit of the latch signal when the x th  bit of the shift signal is at the first state; and 
 a plurality of OR gates, wherein the x th  OR gate receives the x th  bit of the shift signal and the x th  bit of the latch signal, and the compensation control signal is generated according to the outputs of the OR gates. 
 
   
   
     15. The self-calibration circuit for capacitance mismatch as claimed in  claim 14 , wherein the shift register comprises a plurality of delay flip-flops (D flip-flop), each of the D flip-flops receives the clock signal through a clock end, wherein the first D flip-flop has an input end kept at the first state, and provides the first bit of the shift signal through an inverting input; and the x th  D flip-flop of the other D flip-flops receives the (x−1) th  bit of the shift signal through the input end, and provides the x th  bit of the shift signal through a non-inverting input. 
   
   
     16. The self-calibration circuit for capacitance mismatch as claimed in  claim 14 , wherein the latch circuit further comprises a plurality of latches, the x th  latch receives the x th  bit of the shift signal and the comparison signal, outputs the x th  bit of the latch signal, and latches the comparison signal as the x th  bit of the latch signal when the x th  bit of the shift signal is at the first state. 
   
   
     17. The self-calibration circuit for capacitance mismatch as claimed in  claim 14 , wherein the switch control circuit further comprises:
 a first inverter, for receiving a calibration activating signal; 
 a plurality of AND gates, each of the AND gates receiving the output signal of one of the OR gates and the output signal of the first inverter, and outputting one bit of the compensation control signal; and 
 a transition detector, for outputting a reset signal to the shift register and the latch circuit to reset the shift signal and the latch signal when the output signal of the first inverter is changed from the second state to the first state. 
 
   
   
     18. The self-calibration circuit for capacitance mismatch as claimed in  claim 17 , wherein the switch control circuit further comprises:
 a second inverter, for receiving the output signal of the first inverter and outputting a switch control signal; 
 furthermore, the self-calibration circuit for capacitance mismatch further comprising: 
 a first switch, used for connecting a reference voltage and the reference capacitor when the switch control signal is at the first state; and connecting the reference voltage, the compensation capacitor array, and the target capacitor when the switch control signal is at the second state; and 
 a second switch, coupled between the non-inverting input and the inverting input of the comparator; wherein the second switch is turned on when the switch control signal is at the first state, and turned off when the switch control signal is at the second state.