High hysteresis width input circuit

Abstract

The present invention is constructed of a first input circuit having a higher logic level V IH made up of a first inverter circuit 22 controlled by an input signal and an N-type MOSFET 16 controlled by a latch circuit 24 which stores a preceding state, a second input circuit having a lower logic level V IL made up of a second inverter circuit 23 controlled by an input signal and a P-type MOSFET 15 controlled by a latch circuit which stores a preceding state and the latch circuit 24 which stores a preceding state.

1. A high hysteresis width input circuit using MOSFETs, comprising:
 a first inverter circuit provided with a first P-type MOSFET whose source electrode is connected to a power supply of a positive electrode and a first N-type MOSFET whose source electrode is connected to a power supply of a negative electrode, with the respective gate electrodes of said both MOSFETs connected together and the respective drain electrodes connected together; 
 a second inverter circuit provided with a second P-type MOSFET whose source electrode is connected to the power supply of the positive electrode and a second N-type MOSFET whose source electrode is connected to the power supply of the negative electrode, with the respective gate electrodes of said both MOSFETs connected together and the respective drain electrodes connected together; 
 a latch circuit which receives output signals of said first inverter circuit and said second inverter circuit and stores a preceding state until the output signals of both said first and second inverter circuits change when the input signals from said first and second inverter circuits change from a high potential to a low potential or from a low potential to a high potential; 
 a third N-type MOSFET whose drain electrode is connected to the power supply of the positive electrode and whose source electrode is connected to the drain electrode of said first N-type MOSFET; and 
 a third P-type MOSFET whose drain electrode is connected to the power supply of the negative electrode and whose source electrode is connected to the drain electrode of said second P-type MOSFET, 
 the input terminals of said first inverter circuit and said second inverter circuit are connected together to receive an input signal, and 
 the output signal of said latch circuit is extracted outside through an output terminal and input to the gate electrode of said third N-type MOSFET and the gate electrode of said third P-type MOSFET. 
 
   
   
     2. The high hysteresis width input circuit according to  claim 1 , wherein the conductance constant of said third N-type MOSFET is 1 to 4 times the conductance constant of said first N-type MOSFET and the conductance constant of said third P-type MOSFET is 1 to 4 times the conductance constant of said first P-type MOSFET. 
   
   
     3. The high hysteresis width input circuit according to  claim 1 , wherein the conductance constant of said first N-type MOSFET is greater than the conductance constant of said third N-type MOSFET and the conductance constant of said first P-type MOSFET is greater than the conductance constant of said third P-type MOSFET.