On-chip timing characterizer

Abstract

An on-chip timing measurement circuit for improving skew measurement and timing parameter characterization in integrated logic circuits providing increased accuracy and range. The measurement circuit includes a chip delay element characterization circuit for determining chip specific delay values having one output connected to a second control input of the programmable delay generator and receiving an output from the programmable delay generator for providing a value corresponding to the measured chip specific delay element timing, the characterization circuit being enabled by a control signal from the analyzer during a setup phase of the measurement cycle thereby enhancing the accuracy of the measurement for both skew measurement and timing parameter characterization.

1. An on-chip timing measurement circuit for improving skew measurement and timing parameter characterization in integrated logic circuits, comprising:
 a programmable delay circuit having a signal input that receives a first input signal and an output that provides a delayed signal that is a delayed version of said first input signal, the output of said programmable delay circuit being connected to a first input of a circuit under test during timing parameter characterization; 
 a timing analyzer having a first input connected to the output of the programmable delay circuit during skew measurement; a second input connected to receive a second input signal during the skew measurement, the second input signal being connected to a second input of said circuit under test during the timing parameter characterization; a first output connected to a first control input of said programmable delay generator for controlling a delay value of the programmable delay generator; and 
 a second output providing a result of the skew measurement and/or timing parameter characterization; 
 a chip delay element characterization circuit for determining chip specific delay values having one output connected to a second control input of said programmable delay generator and receiving an output from said programmable delay generator for providing a value corresponding to a measured chip specific delay element timing, said characterization circuit being enabled by a control signal from said analyzer during a setup phase. 
 
   
   
     2. An on-chip timing measurement circuit as claimed in  claim 1  wherein said programmable delay circuit comprises:
 a major scale delay circuit that includes a chain of delay elements each providing a circuit delay value; 
 an accurate scale delay circuit that includes a chain of delay elements each providing a fractional unit delay value, the accurate scale delay circuit having an input connected to an output of the major scale delay circuit; and 
 an output logic circuit connected to an output of the accurate scale delay circuit so as to provide a wide range of delay values and a programmable output signal polarity. 
 
   
   
     3. An on-chip timing measurement circuit as claimed in  claim 1  wherein said delay element characterization circuit comprises a logic circuit for configuring delay elements of the programmable delay generator to form a ring oscillator so as to derive a unit delay value of the circuit under test from an oscillation frequency of the ring oscillator. 
   
   
     4. An on-chip timing measurement circuit as claimed in  claim 1  wherein said analyzer is a logic circuit that compares an output of the circuit under test with an expected output during timing parameter characterization whereas the analyzer compares transitions of the input signals during the skew measurement. 
   
   
     5. The on-chip timing measurement circuit of  claim 1 , wherein one of the inputs of the timing analyzer is connected to an output of the circuit under test during timing parameter characterization. 
   
   
     6. The on-chip timing measurement circuit of  claim 5 , wherein the timing analyzer compares an output of the circuit under test with an expected output during timing parameter characterization. 
   
   
     7. The on-chip timing measurement circuit of  claim 1 , wherein the timing analyzer is structured to compare a transition of the first input signal with a transition of the second input signal during skew measurement. 
   
   
     8. The on-chip timing measurement circuit of  claim 1 , wherein the second output provides the result of the skew measurement and/or timing parameter characterization in digital format. 
   
   
     9. An on-chip method for measuring skew and timing characteristics of integrated circuits providing increased accuracy and range, comprising the steps of:
 providing a programmable delay to a first input signal, thereby producing a delayed signal; 
 connecting said delayed signal to a first input of a circuit under test in a case of timing parameter characterization, whereas connecting the delayed signal to a first input of a timing analyzer in a case of skew measurement; 
 supplying a second input signal to a second input of said circuit under test in the case of timing parameter characterization whereas supplying said second input signal to a second input of said analyzer in the case of skew measurement; automatically adjusting the programmable delay using a first output of said analyzer; 
 receiving a result of the skew measurement and/or timing parameter characterization from a second output of said analyzer; and 
 characterizing chip specific delays by connecting a chain of delay elements that provides the programmable delay as a ring counter and deriving a unit delay value from an oscillation frequency of the ring counter, during a setup phase. 
 
   
   
     10. An on-chip method for measuring skew and timing characteristics of integrated circuits as claimed in  claim 9  wherein said step of providing the programmable delay comprises the steps of:
 providing a major scale delay circuit having of a chain of delay elements for delaying the first input signal by a first delay value; and 
 providing an accurate scale delay circuit having a chain of delay elements for delaying said first input signal by a second delay value, said second delay value being a fractional part of a unit delay value of said first delay value. 
 
   
   
     11. The method of  claim 9  further including comparing an output of the circuit under test with an expected output during timing parameter characterization. 
   
   
     12. The method of  claim 9  further including comparing a transition of the first input signal with a transition of the second input signal during skew measurement. 
   
   
     13. The method of  claim 9  further including connecting an input of the timing analyzer to an output of the circuit under test during timing parameter characterization. 
   
   
     14. The method of  claim 9  further comprising, after receiving the result of the skew measurement from the analyzer, using that result during timing parameter characterization. 
   
   
     15. The method of  claim 9  wherein the result of the skew measurement and/or timing parameter characterization is received in digital format. 
   
   
     16. An on-chip timing measurement circuit for improving skew measurement in integrated logic circuits, comprising:
 a programmable delay circuit having a signal input that receives a first input signal, a control input, and an output that provides a delayed signal that is a delayed version of said first input signal, and 
 a skew analyzer having a first input connected to the output of the programmable delay circuit; a second input connected to receive a second input signal; a first output connected to the control input of the programmable delay generator for controlling a delay value of the programmable delay generator, and a second output, the skew analyzer being structured to measure a skew between the delayed signal and the second input signal, iteratively adjust the delay value until the skew is substantially zero, and output a value on the second output that reflects a skew between the first and second input signals. 
 
   
   
     17. The on-chip timing measurement circuit of  claim 16 , wherein the programmable delay circuit comprises
 a major scale delay circuit that includes a chain of delay elements each providing a circuit delay value; 
 an accurate scale delay circuit that includes a chain of delay elements each providing a fractional unit delay value, the accurate scale delay circuit having an input connected to an output of the major scale delay circuit; and 
 an output logic circuit connected to an output of the accurate scale delay circuit so as to provide a wide range of delay values and a programmable output signal polarity. 
 
   
   
     18. The on-chip timing measurement circuit of  claim 17 , wherein the circuit delay value provided by each of the delay elements in the chain of delay elements of the major scale delay circuit is less than the total of the fractional unit delay values provided by the chain of delay elements of the accurate scale delay circuit. 
   
   
     19. The on-chip timing measurement circuit of  claim 16 , further comprising a delay element characterization circuit comprises a logic circuit for configuring delay elements of the programmable delay generator to form a ring oscillator so as to derive a unit delay value of a circuit under test from an oscillation frequency of the ring oscillator. 
   
   
     20. The on-chip timing measurement circuit of  claim 16  wherein said analyzer is a logic circuit that compares an output of the circuit under test with an expected output during timing parameter characterization whereas the analyzer compares transitions of the input signals during the skew measurement.