Power-on-reset circuit based on the threshold levels and quadratic I-V behavior of MOS transistors

Abstract

A system and method for providing a clock-independent reset signal based on supply voltage threshold levels is described. The trip points or predefined voltage levels where the power-on-reset circuit behavior reverses (which controls the reset signal) is determined by the dimensions of the transistors selected for the voltage dividers. The system and method described allows for a clock-independent stable power-up phase while consuming a very small area of a circuit board and, in particular, on integrated circuits.

1. A processor system comprising:
 a processor; and 
 a clock-independent power-on-reset circuit coupled to said processor, said clock-independent power-on-reset circuit comprising:
 a first voltage divider connected to a supply voltage; 
 a second voltage divider connected to said supply voltage, said second voltage divider comprising a pair of high threshold PMOS transistors and a resistive element; 
 an amplifier coupled to said first and second voltage dividers, wherein said amplifier is a high gain amplifier in an open loop configuration and includes a differential stage having an output coupled to an even plurality of coupled asymmetrical inverters in addition to a coupled pair of asymmetrical inverters of said amplifier; and 
 a feedback circuit for feeding back an output of the amplifier to said input of the amplifier. 
 
 
   
   
     2. The system of  claim 1 , wherein said pair of asymmetrical inverters comprises a first asymmetrical inverter and a second asymmetrical inverter coupled to each other, said first asymmetrical inverter having an input coupled to an output of said differential stage and an output coupled to an input of said second asymmetrical inverter. 
   
   
     3. The system of  claim 1 , wherein said second voltage divider provides an inverting input to said differential stage. 
   
   
     4. The system of  claim 1 , wherein said second voltage divider is a PMOS voltage divider and said resistive element comprises a low threshold long PMOS transistor. 
   
   
     5. The system of  claim 1 , wherein said differential stage further comprises a plurality of PMOS transistors and a plurality of NMOS transistors and one of said plurality of NMOS transistors forces the output of said differential stage low at supply voltages close to ground. 
   
   
     6. The system of  claim 1 , wherein said feedback circuit comprises a pair of NMOS transistors. 
   
   
     7. The system of  claim 1 , wherein each of said asymmetrical inverters comprises a NMOS transistor and a PMOS transistor and each asymmetrical inverter accepts an input signal, inverts said input signal, amplifies a voltage level of said input signal and sharpens said input signal. 
   
   
     8. The system of  claim 1 , wherein said feedback circuit provides hysteresis to stabilize said high gain open loop mode amplifier. 
   
   
     9. The system of  claim 1 , wherein said high gain amplifier in open loop mode operates as a comparator. 
   
   
     10. A processor system comprising:
 a processor; 
 an integrated circuit coupled to said processor; and 
 a clock-independent power-on-reset circuit coupled to said integrated circuit, said clock-independent power-on-reset circuit comprising:
 a first voltage divider connected to a supply voltage, said first voltage divider comprising a pair of high threshold short NMOS transistors and a resistor; 
 a second voltage divider connected to said supply voltage; 
 an amplifier coupled to said first and second voltage dividers, wherein said amplifier is a high gain amplifier in an open loop configuration and includes a differential stage having an output coupled to a first one of a coupled pair of asymmetrical inverters, wherein said high gain amplifier in open loop mode operates as a comparator; and 
 a feedback circuit for feeding back an output of the amplifier to an input of the amplifier. 
 
 
   
   
     11. The system of  claim 10 , wherein said resistor functions as a low threshold long NMOS transistor. 
   
   
     12. The system of  claim 10 , wherein said pair of high threshold short NMOS transistors are connected in series and operate as a single high threshold transistor. 
   
   
     13. A system comprising:
 an integrated circuit; and 
 a power-on-reset circuit connected to the integrated circuit, said power-on reset circuit comprising:
 a first voltage divider connected to a supply voltage, wherein the first voltage divider is an NMOS voltage divider; 
 a second voltage divider connected to said supply voltage; 
 an open loop mode high gain amplifier having non-inverting and inverting inputs for receiving outputs from said first and second voltage dividers respectively, said open loop mode high gain amplifier further comprises a differential stage, wherein said differential stage is coupled to said first voltage divider and further coupled to said second voltage divider, and a pair of coupled asymmetrical inverters; 
 a feedback circuit for feeding back an output signal to said non-inverting input of said open loop mode amplifier, wherein said feedback circuit provides hysteresis to stabilize said high gain open loop mode amplifier; and 
 an even plurality of coupled asymmetrical inverters in addition to the pair of coupled asymmetrical inverters of said amplifier. 
 
 
   
   
     14. The system of  claim 13 , wherein said open loop mode amplifier operates as a comparator. 
   
   
     15. The system of  claim 13 , wherein said differential stage further comprises a plurality of PMOS transistors and a plurality of NMOS transistors, wherein one of said plurality of NMOS transistors forces the output of said differential stage low at very low supply voltages. 
   
   
     16. The system of  claim 13 , wherein said feedback circuit comprises a pair of NMOS transistors. 
   
   
     17. The system of  claim 13 , wherein each of said asymmetrical inverters comprises a NMOS transistor and a PMOS transistor and each asymmetrical inverter accepts an input signal, inverts said input signal, amplifies a voltage level of said input signal and sharpens said input signal. 
   
   
     18. A processor system comprising:
 a processor; and 
 a clock-independent power-on-reset circuit coupled to said processor, said clock-independent power-on-reset circuit comprising:
 a NMOS voltage divider connected to a supply voltage; 
 a PMOS voltage divider connected to said supply voltage; 
 an open loop mode high gain amplifier having non-inverting and inverting inputs for receiving outputs from said NMOS and PMOS voltage dividers respectively, said amplifier comprising asymmetrical inverters; and 
 a feedback circuit for feeding back an output signal to said non-inverting input of said open loop mode amplifier; and 
 an even plurality of coupled asymmetrical inverters in addition to the coupled pair of asymmetrical inverters of said amplifier. 
 
 
   
   
     19. The system of  claim 18 , further comprising a feedback circuit coupled to said first voltage divider and coupled to an output of said comparison circuit, said feedback circuit further coupled to said supply voltage. 
   
   
     20. The system of  claim 19 , wherein said feedback circuit comprises a pair of NMOS transistors.