Fractional-N frequency synthesizer with sigma-delta modulator for variable reference frequencies

Abstract

A frequency synthesizer includes: a phase detector, a loop filter, a controllable oscillator, a frequency divider, and a sigma-delta modulator for providing the division factor according to an integral part and a fractional part. The sigma-delta modulator includes a controller for providing a first digital value, a second digital value and a third digital value; a first adder for combining the second digital value, the third digital value, and a digital feedback value to generate a combination result; a quantizer for quantizing the combination result to generate a quantization value; a second adder for combining the first digital value and the quantization value to generate the division factor; and a multiplier for multiplying the quantization value by a constant multiplication factor; wherein the controller adjusts the third digital value in response to the reference signal for making an output frequency resolution substantially fixed.

1. A frequency synthesizer, comprising:
 a phase detector, coupled to a reference signal and a feedback signal, for generating a phase difference signal representing a phase difference between the reference signal and the feedback signal; 
 a loop filter, coupled to the phase detector, for filtering the phase difference signal and generating a control voltage; 
 a controllable oscillator, coupled to the loop filter, for generating an output signal according to the control voltage; 
 a frequency divider, coupled to the controllable oscillator and the phase detector, for dividing the frequency of the output signal according to a division factor to generate the feedback signal; and 
 a sigma-delta modulator, coupled to the frequency divider, for providing the division factor according to an integral part and a fractional part, the sigma-delta modulator comprising:
 a controller for providing a first digital value, a second digital value and a third digital value, wherein the first digital value represents the integral part, the second digital value represents a first portion of the fractional part, and the third digital value represents a second portion of the fractional part; 
 a first adder, coupled to the controller, for combining the second digital value, the third digital value, and a digital feedback value to generate a combination result; 
 a low-pass filter, coupled to the first adder, for outputting a filtering result according to the combination result; 
 a quantizer, coupled to the low-pass filter, for quantizing the filtering result to generate a quantization value; 
 a second adder, coupled to the quantizer, for combining the first digital value and the quantization value to generate the division factor; and 
 a multiplier, coupled to the first adder and the quantizer, for multiplying the quantization value by a constant multiplication factor; 
 
 
     wherein the controller adjusts the third digital value in response to the reference signal for making an output frequency resolution substantially fixed. 
   
   
     2. The frequency synthesizer of  claim 1 , wherein the controller determines the first digital value N, the second digital value FE, and the third digital value FER by the following equations:
     N=F   out   /F   ref ; 
     FE ={[Mod( F   out   ,F   ref )]× CB}/F   ref ; and 
     FER =Mod{{[Mod( F   out   ,F   ref )]× CB},F   ref }; 
 
     where F out  represents the frequency of the output signal, F ref  represents the frequency of the reference signal, CB represents the constant multiplication factor, and Mod{ } represents a modulo operation. 
   
   
     3. The frequency synthesizer of  claim 1 , wherein the controller determines the first digital value N, the second digital value FE, and the third digital value FER by the following equations:
     N=F   out   /F   ref ; 
     FE ={[Mod( F   out   ,F   ref )]× CB}/F   ref ; and 
     FER ={Mod{{[Mod( F   out   ,F   ref )]× CB},F   ref }}*2 R   /F   ref ; 
 
     where F out  represents the frequency of the output signal, F ref  represents the frequency of the reference signal, CB represents the constant multiplication factor, R is an integer, and Mod{ } represents a modulo operation. 
   
   
     4. The frequency synthesizer of  claim 1 , wherein the sigma-delta modulator further comprises a dithering circuit, coupled to the controller, for receiving the third digital value and generating a dithering value according to the received third digital value; and the first adder combines the dithering value, the second digital value, and the digital feedback value to generate the combination result. 
   
   
     5. A frequency synthesizing method, comprising:
 generating a control voltage according to a phase difference between a reference signal and a feedback signal; 
 generating an output signal according to the control voltage; 
 dividing the frequency of the output signal according to a division factor to generate the feedback signal; and 
 providing the division factor according to an integral part and a fractional part by:
 providing a first digital value, a second digital value and a third digital value, wherein the first digital value represents the integral part, the second digital value represents a first portion of the fractional part, and the third digital value represents a second portion of the fractional part; 
 combining the second digital value, the third digital value, and a digital feedback value to generate a combination result; 
 filtering the combination result for outputting a filtering result; 
 quantizing the filtering result to generate a quantization value; 
 combining the first digital value and the quantization value to generate the division factor; 
 multiplying the quantization value by a constant multiplication factor; and 
 adjusting the third digital value in response to the reference signal for making an output frequency resolution substantially fixed. 
 
 
   
   
     6. The frequency synthesizing method of  claim 5 , wherein the step of providing the first digital value, the second digital value and the third digital value comprises:
 determining the first digital value N, the second digital value FE, and the third digital value FER by the following equations:
     N=F   out   /F   ref ; 
     FE ={[Mod( F   out   ,F   ref )]* CB}/F   ref ; and 
     FER =Mod{{[Mod( F   out   ,F   ref )]* CB},F   ref }; 
 
 
     where F out  represents the frequency of the output signal, F ref  represents the frequency of the reference signal, CB represents the constant multiplication factor, and Mod{ } represents a modulo operation. 
   
   
     7. The frequency synthesizing method of  claim 5 , wherein the step of providing the first digital value, the second digital value and the third digital value comprises:
 determining the first digital value N, the second digital value FE, and the third digital value FER by the following equations:
     N=F   out   /F   ref ; 
     FE ={[Mod( F   out   ,F   ref )]* CB}/F   ref ; and 
     FER ={Mod{{[Mod( F   out   ,F   ref )]* CB},F   ref }}*2 R   /F   ref ; 
 
 
     where F out  represents the frequency of the output signal, F ref  represents the frequency of the reference signal, CB represents the constant multiplication factor, R is an integer, and Mod{ } represents a modulo operation. 
   
   
     8. The frequency synthesizing method of  claim 5 , wherein the step of providing the division factor further comprises:
 receiving the third digital value and generating a dithering value according to the received third digital value; and 
 the step of generate the combination result comprises: 
 combining the dithering value, the second digital value, and the digital feedback value to generate the combination result.