Semiconductor device and method for fabricating the same

Abstract

Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed higher than the main surface of the semiconductor substrate and the trench gate conductive layer and gate insulating film are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench. In this method, a trench wherein a trench-gate is to be formed is formed on the main surface of the semiconductor substrate with the insulating film formed thereon with a mask; and the side surface of the insulating film is caused to retreat from the upper end of the trench by isotropic etching, whereby a gate insulating film and a conductive layer to be the trench gate are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench. According to the present invention, occurrence of a source offset and damage of a gate insulating film can be prevented.

1. A method for fabricating a semiconductor device including a plurality of trench-gate type MISFETs, comprising the steps of:
 (a) preparing a semiconductor substrate having a main surface including a first region and a second region; 
 (b) forming an insulating film over the main surface of the semiconductor substrate; 
 (c) forming first openings and a second opening in the insulating film in the first and second regions respectively; 
 (d) etching the main surface of the semiconductor substrate using the insulating film as a mask to form first trenches and a second trench in the semiconductor substrate; 
 (e) etching side surfaces of the first and second openings of the insulating film to enlarge the first and second openings, thereby exposing the main surface of the semiconductor substrate at the periphery of the first and second trenches, 
 (f) after the step (e), forming oxide films over surfaces inside and at peripheries of the first and second trenches of the semiconductor substrate, with the insulating film remaining over the main surface of the semiconductor substrate; 
 (g) after the step (f), forming a conductive layer over the insulating film and the oxide film inside and at the periphery of the trench in the first and second regions; 
 (h) patterning the conductive layer to form gate electrodes of the plurality of MISFETs and a gate wiring in the first and second regions respectively, with the insulating film remaining over the main surface of the semiconductor substrate, 
 (i) after the step (h), removing a portion of the insulating film in the first region, 
 (j) introducing first impurities into the semiconductor substrate to form channel-forming regions of the plurality of MISFETs in the first region; and 
 (k) introducing second impurities into the semiconductor substrate to form source regions of the plurality of MISFETs over the channel-forming regions in the first region, 
 wherein the gate electrodes and gate wiring are connected, 
 wherein the source regions of the plurality MISFETs are electrically connected; 
 the channel-forming regions of the plurality MISFETs are electrically connected; and 
 the plurality of MISFETs comprise a power MOSFET. 
 
   
   
     2. A method according to  claim 1 , wherein a drain region of the plurality of the MISFETs is formed in the semiconductor substrate; and
 the drain region is positioned under the channel-forming regions. 
 
   
   
     3. A method according to  claim 1 , wherein in the step (h), top surfaces of the gate electrodes are higher than the main surface of the semiconductor substrate. 
   
   
     4. A method according to  claim 1 , wherein the conductive layer is comprised of polycrystalline silicon. 
   
   
     5. A method according to  claim 1 , wherein after the step (i), a portion of the insulating film remains under the gate wiring in the second region. 
   
   
     6. A method according to  claim 5 , wherein a drain region of the plurality of the MISFETs is formed in the semiconductor substrate; and
 the drain region is positioned under the channel-forming regions. 
 
   
   
     7. A method according to  claim 5 , wherein in the step (h), top surfaces of the gate electrodes are higher than the main surface of the semiconductor substrate. 
   
   
     8. A method according to  claim 5 , wherein the first trenches are connected. 
   
   
     9. A method according to  claim 5 , wherein the first trenches are disposed in parallel. 
   
   
     10. A method according to  claim 1 , further comprising the steps of:
 (l) forming an interlayer insulating film over the gate electrodes and the gate wiring, 
 (m) forming a first wiring and a second wiring over the interlayer insulating film, 
 wherein the first and second wiring are electrically connected to the source region and the gate wiring respectively. 
 
   
   
     11. A method according to  claim 10 , wherein the first and the second wiring are comprised of a same material. 
   
   
     12. A method according to  claim 1 , wherein the oxide film is comprised of a thermal oxide film. 
   
   
     13. A method according to  claim 1 , wherein the insulating film is formed by a thermal oxidation method. 
   
   
     14. A method according to  claim 1 , wherein the first trenches are connected; and
 the second trench is connected with the first trenches. 
 
   
   
     15. A method according to  claim 1 , wherein the first trenches are disposed in parallel. 
   
   
     16. A method for fabricating a semiconductor device including a plurality of trench-gate type MISFETs, comprising the steps of:
 (a) preparing a semiconductor substrate having a main surface; 
 (b) forming an insulating film over the main surface of the semiconductor substrate; 
 (c) forming first openings in the insulating film; 
 (d) etching the main surface of the semiconductor substrate using the insulating film as a mask to form first trenches in the semiconductor substrate; 
 (e) etching side surfaces of the first openings of the insulating film to enlarge the first openings, thereby exposing the main surface of the semiconductor substrate at the periphery of the first trenches, 
 (f) after the step (e), forming oxide films over surfaces inside and at peripheries of the first trenches of the semiconductor substrate, with the insulating film remaining over the main surface of the semiconductor substrate; 
 (g) after the step (f), forming a conductive layer over the insulating film and the oxide film inside and at the periphery of the trench; 
 (h) patterning the conductive layer to form gate electrodes of the plurality of MISFETs, with the insulating film remaining over the main surface of the semiconductor substrate, 
 (i) after the step (h), removing a portion of the insulating film; 
 (j) introducing first impurities into the semiconductor substrate to form channel-forming regions of the plurality of MISFETs; and 
 (k) introducing second impurities into the semiconductor substrate to form source regions of the plurality of MISFETs over the channel-forming regions; 
 wherein the source regions of the plurality MISFETs are electrically connected; 
 the channel-forming regions of the plurality MISFETs are electrically connected; and 
 the plurality of MISFETs comprise a power MOSFET.