Sigma-delta analog-to-digital converter and method for reducing harmonics

Abstract

An arrangement ( 100 ) and method for sigma-delta analog-to-digital conversion by providing parallel translating sigma-delta analog-to-digital converters ( 21, 22 ) and summing their outputs to produce a digital output signal having a bandwidth greater than that of the first or second translating sigma-delta analog-to-digital converters ( 21, 22 ). The parallel translating sigma-delta analog-to-digital converters ( 21, 22 ) use switching sequences arranged to cancel third and fifth harmonics in the digital output signal. Orthogonality error in the switching sequences applied to the sigma-delta modulators is compensated by adjusting the phase of the signals applied to mixers ( 51, 52 ).

1. A sigma-delta analog-to-digital converter arrangement comprising:
 first translating sigma-delta analog-to-digital converter for receiving an analog signal for translation from an input bandwidth and input frequency to a reduced bandwidth frequency band with a first phase shift and conversion to a first digital signal; 
 first mixer reverse frequency translating a processed first digital signal; second translating sigma-delta analog-to-digital converter for receiving the analog signal for translation from an input bandwidth and input frequency to a reduced bandwidth frequency band with a second phase shift and conversion to a second digital signal; 
 second mixer reverse frequency translating a processed second digital signal; and 
 a summer for summing reverse frequency translated processed digital signals to produce a digital output signal at the input bandwidth and input frequency 
 wherein the first and second translating sigma-delta analog-to-digital converters comprise switched capacitors arranged to use switching sequences that produce reduced third and fifth harmonics in the digital output signal. 
 
     
     
       2. The arrangement of  claim 1 , wherein the first phase shift and the second phase shift are in quadrature or almost in quadrature. 
     
     
       3. The arrangement of  claim 2 , further comprising means for adjusting for quadrature errors between signals in the first and second translating sigma-delta analog-to-digital converters. 
     
     
       4. The arrangement of  claim 1 , wherein the first and second translating sigma-delta analog-to-digital converters each comprise a multiplicity of capacitors of substantially equal value or a multiplicity of capacitors of whose values are in a binary-weighted relationship. 
     
     
       5. The arrangement of  claim 1 , wherein the switching sequences comprise unit coefficients. 
     
     
       6. The arrangement of  claim 1 , wherein the switching sequences comprise binary-weighted coefficients. 
     
     
       7. The arrangement of  claim 1 , further comprising:
 first decimation filtering and down-sampler and first DC notch filter coupled between the output of the first translating sigma-delta analog-to-digital converters and the summer; and 
 second decimation filter and down-sampler and second DC notch filter coupled between the output of the second translating sigma-delta analog-to-digital converter and the summer. 
 
     
     
       8. The arrangement of  claim 1 , wherein the first and second mixer means are arranged to produce reverse first and second phase shifts in quadrature or almost in quadrature to compensate for quadrature error present between the phase shifts introduced in first and second translating sigma-delta analog-to-digital converter means respectively. 
     
     
       9. The arrangement of  claim 1 , arranged for use in a wideband CDMA wireless communication system. 
     
     
       10. The arrangement of  claim 1  arranged for use in a multi-standard wireless communication system. 
     
     
       11. An integrated circuit comprising the arrangement of  claim 1 . 
     
     
       12. A method for sigma-delta analog-to-digital conversion comprising: providing first translating sigma-delta analog-to-digital converter receiving an analog signal, translating from an input bandwidth and input frequency to a reduced bandwidth frequency band with a first phase shift and converting to a first digital signal;
 reverse frequency translating a processed first digital signal; providing second translating sigma-delta analog-to-digital converter receiving the analog signal, translating from an input bandwidth and input frequency to a reduced bandwidth frequency band with a second phase shift and converting to a second digital signal; 
 reverse frequency translating a processed second digital signal; and summing reverse frequency translated processed digital signals to produce a digital output signal at the input bandwidth and input frequency, 
 wherein the steps of reverse frequency translating comprise using switching sequences that produce reduced third and fifth harmonics in the digital output signal. 
 
     
     
       13. The method of  claim 12 , wherein the first phase shift and the second phase shift are in quadrature or almost in quadrature. 
     
     
       14. The method of  claim 12 , wherein the step of using switching sequences comprises using unit coefficients. 
     
     
       15. The method of  claim 12 , wherein the step of using switching sequences comprises using binary-weighted coefficients. 
     
     
       16. The method of  claims 12 , further comprising adjusting for quadrature errors between signals applied to the first and second translating sigma-delta analog-to-digital converters. 
     
     
       17. The method of  claim 12 , further comprising:
 providing first decimation filtering and down-sampling, first DC notch filtering and a first mixer between the output of the first translating sigma-delta analog-to-digital converter and the summer; and 
 providing second decimation filtering and down-sampling, second DC notch filtering and second mixer between the output of the second translating sigma-delta analog-to-digital converter and the summer. 
 
     
     
       18. The method of  claim 12 , wherein the step of reverse frequency translating a processed digital signal is performed in quadrature or almost in quadrature to compensate for quadrature error present between the phase shifts introduced in first and second translating sigma-delta analog-to-digital converter respectively. 
     
     
       19. The method of  claim 12 , used in a wideband CDMA wireless communication system.