Operational transconductance amplifier with DC offset elimination and low mismatch

Abstract

Provided is a transconductor capable of eliminating a direct current (DC) offset component of a signal and compensating a mismatch of the signal. The transconductor includes amplifiers of simple circuit structures, and a common mode control DC offset elimination circuit. The transconductor includes a common mode control DC offset elimination circuit unit receiving input/output voltages to stabilize the current supplying and the output DC value, a first amplifier and a second amplifier reducing a mismatch in a transconductor circuit and increasing an output resistance, in order to prevent a signal distortion or a wrong operation of the circuit that is caused by the mismatch signal and unstable DC voltage.

1. A transconductor comprising:
 a transconductor circuit outputting an output voltage that is converted from an input voltage so as to be in proportion to a transconductance; and 
 a direct current (DC) offset elimination circuit fixing an output DC voltage, which is changed according to a DC offset included in the input voltage, into a common mode voltage of constant magnitude, 
 wherein the transconductor circuit including:
 a first transistor having a dual-pair input structure and operating in a triode region; 
 a second transistor receiving a node voltage of the first transistor and controlling a drain-source voltage of the first transistor so that the first transistor can operate in the triode region and a first inversion amplifier, 
 a third transistor and a second inversion amplifier disposed to increase an output resistance; and 
 a fourth transistor supplying the electric current that is input from the DC offset elimination circuit by mirroring the current. 
 
 
   
   
     2. The transconductor of  claim 1 , wherein the first and second transistors are n-channel type MOS transistors, and the third and fourth transistors are p-channel type MOS transistors. 
   
   
     3. The transconductor of  claim 1 , wherein the DC offset elimination circuit receives one or more input voltages from the transconductor circuit to generate a common current that is a function of the input voltages, and generates DC offset elimination voltage by combining the common current with a signal that is formed by amplifying a difference between the output voltage and the common mode voltage. 
   
   
     4. The transconductor of  claim 3 , wherein the DC offset elimination circuit includes a current generation circuit having a transistor and an amplifier to generate the common current, a common mode feedback circuit including two differential amplifiers, and a load circuit having a transistor functioning as a current mirror. 
   
   
     5. The transconductor of  claim 1 , wherein the first inversion amplifier includes a differential amplifier receiving voltages at symmetric both nodes of the transconductor circuit. 
   
   
     6. The transconductor of  claim 1 , wherein the first inversion amplifier receives the drain voltage of the first transistor so that the first transistor can operate in the triode region. 
   
   
     7. The transconductor of  claim 5 , wherein the first inversion amplifier includes: a first n-channel type MOS transistor operating in the triode region, a second n-channel type MOS transistor receiving a node voltage through the gate sharing the same node as that of the drain of the first n-channel type MOS transistor, a third n-channel type MOS transistor performing an inversion amplification by receiving a signal that is input into the source of the second n-channel type MOS transistor and common gate amplified through the gate of itself, and a fourth n-channel type MOS transistor receiving the inversion amplified signal through the gate and sharing the source with the node. 
   
   
     8. The transconductor of  claim 1 , wherein the second inversion amplifier includes an inversion feedback differential amplifier receiving the common mode control voltage to generate currents. 
   
   
     9. The transconductor of  claim 7 , wherein the inversion feedback differential amplifier includes a p-channel type MOS transistor receiving the common mode control voltage to generate the current, a fifth n-channel type MOS transistor receiving the drain voltage of the p-channel type MOS transistor and buffering the voltage from the gate to the source, and a sixth n-channel type MOS transistor differentially amplifying the voltage buffered by the fifth n-channel type MOS transistor and inputting the amplified voltage into the gate of the third transistor.