Systems and methods for creating complex poles

Abstract

Various devices, circuits and systems including filter sections for creating complex poles are described herein. For example, various circuits including transistors, tuning capacitors and resistors are described. In the circuits, the tuning capacitor is electrically coupled between the gate and source of the transistor, and the resistor is electrically coupled to the gate of the transistor. In one configuration, the circuit input is applied to the gate of the transistor via the resistor, and the output is taken from the source of the transistor. In another configuration, the input is applied to the source of the transistor, and the output is taken from the same source. In yet another configuration, the input is applied at the source of the transistor and the output is taken from the drain of the transistor.

1. A differential, tunable circuit operable to create a pair of complex poles the circuit comprising:
 a first transistor with a gate, a source and a drain; 
 a first tuning capacitor wherein the first tuning capacitor is electrically coupled between the gate of the first transistor and the source of the first transistor; 
 a first resistor, wherein the first resistor is electrically coupled to the gate of the first transistor, and wherein a first input is electrically coupled to the gate of the first transistor via the first resistor; 
 a second transistor with a gate, a source and a drain; 
 a second tuning capacitor, wherein the second tuning capacitor is electrically coupled between the gate of the second transistor and the source of the second transistor; and 
 a second resistor, wherein the second resistor is electrically coupled to the gate of the second transistor, and wherein a second input is electrically coupled to the gate of the second transistor via the second resistor. 
 
   
   
     2. The circuit of  claim 1 , wherein the first input is a first bias input, wherein the second input is a second bias input, wherein a differential signal input is applied across the source of the first transistor and the source of the second transistor, and wherein a differential output of the differential circuit is electrically coupled to nodes selected from a group consisting of: the source of the first transistor and the source of the second transistor; and the drain of the first transistor and the drain of the second transistor. 
   
   
     3. The circuit of  claim 1 , wherein the differential circuit further comprises:
 a third capacitor electrically coupled between the source of the first transistor and the source of the second transistor. 
 
   
   
     4. The circuit of  claim 3 , wherein the first transistor is a first filter transistor, wherein the second transistor is a second filter transistor, and wherein the differential circuit further comprises:
 a first common gate transistor with a gate, a drain and a source; 
 a second common gate transistor with a gate, a drain and a source; 
 a first differential input transistor with a gate, a drain and a source; 
 a second differential input transistor with a gate, a drain and a source; 
 a third filter transistor with a gate, a drain and a source; 
 a third tuning capacitor, wherein the third tuning capacitor is electrically coupled between the gate of the third filter transistor and the source of the third filter transistor; 
 a fourth filter transistor with a gate, a drain and a source; 
 a fourth tuning capacitor, wherein the fourth tuning capacitor is electrically coupled between the gate of the fourth filter transistor and the source of the fourth filter transistor; 
 a first differential input electrically coupled to the gate of the first differential input transistor; 
 a second differential input electrically coupled to the gate of the second differential input transistor; 
 wherein the drain of the first differential input transistor is electrically coupled to the source of the third filter transistor wherein the drain of the second differential input transistor is electrically coupled to the source of the fourth filter transistor; 
 wherein the drain of the third filter transistor is electrically coupled to the source of the first common gate transistor; 
 wherein the drain of the fourth filter transistor is electrically coupled to the source of the second common gate transistor; 
 wherein the drain of the first common gate transistor is electrically coupled to the source of the first filter transistor; 
 wherein the drain of the second common gate transistor is electrically coupled to the source of the second filter transistor; and wherein the differential circuit is operable to create two pairs of complex poles. 
 
   
   
     5. The circuit of  claim 1 , wherein the differential circuit further comprises:
 a third capacitor, wherein the third capacitor is electrically coupled to the source of the first transistor; and 
 a fourth capacitor, wherein the fourth capacitor is electrically coupled to the source of the second transistor. 
 
   
   
     6. The circuit of  claim 1 , wherein the differential circuit further comprises:
 a first output electrically coupled to the source of the first transistor; 
 a second output electrically coupled to the source of the second transistor; and 
 a nullator electrically coupled between the source of the first transistor and the source of the second transistor. 
 
   
   
     7. The circuit of  claim 6 , wherein the nullator includes:
 a third transistor with a gate, a source and a drain; 
 a fourth transistor with a gate, a source and a drain; 
 wherein the drain of the third transistor is electrically coupled to the gate of the fourth transistor, wherein the drain of the fourth transistor is electrically coupled to the gate of the third transistor; and 
 wherein the nullator is electrically coupled between the source of the first transistor and the source of the second transistor by electrically coupling the drain of the third transistor with the source of the first transistor and electrically coupling the drain of the fourth transistor to the source of the second transistor. 
 
   
   
     8. The circuit of  claim 1 , wherein the differential circuit further comprises:
 a first cross-coupling capacitor, wherein the first cross-coupling capacitor is electrically coupled between the gate of the first transistor and the second input; and 
 a second cross-coupling capacitor, wherein the second cross-coupling capacitor is electrically coupled between the gate of the second transistor and the first input. 
 
   
   
     9. The circuit of  claim 1 , wherein the first transistor is a first filter transistor, wherein the second transistor is a second filter transistor, and wherein the differential circuit further comprises:
 a first load stage transistor with a gate, a source and a drain; 
 a second load stage transistor with a gate, a source and a drain; 
 wherein the drain of the first load stage transistor is electrically coupled to a power source, wherein the gate of the first load stage transistor is electrically coupled to a first bias input, wherein the source of the first load stage transistor is electrically coupled to the drain of the first filter transistor, and wherein a first output of the circuit is electrically coupled to the drain of the first filter transistor; and 
 wherein the drain of the second load stage transistor is electrically coupled to the power source, wherein the gate of the second load stage transistor is electrically coupled to a second bias input, wherein the source of the second load stage transistor is electrically coupled to the drain of the second filter transistor, and wherein a second output of the circuit is electrically coupled to the drain of the second filter transistor. 
 
   
   
     10. The circuit of  claim 9 , wherein the differential circuit further comprises:
 a first differential input transistor with a gate, a drain and a source; 
 a second differential input transistor with a gate, a drain and a source; 
 a first differential input electrically coupled to the gate of the first differential input transistor; 
 a second differential input electrically coupled to the gate of the second differential input transistor; 
 wherein the drain of the first differential input transistor is electrically coupled to the source of the first filter transistor; and 
 wherein the drain of the second differential input transistor is electrically coupled to the source of the second filter transistor. 
 
   
   
     11. The circuit of  claim 1 , wherein the first transistor is a first filter transistor, wherein the second transistor is a second filter transistor, and wherein the differential circuit further comprises:
 a first differential input transistor with a gate, a drain and a source; 
 a second differential input transistor with a gate, a drain and a source; 
 a first differential input electrically coupled to the gate of the first differential input transistor; 
 a second differential input electrically coupled to the gate of the second differential input transistor; 
 wherein the drain of the first differential input transistor is electrically coupled to the source of the first filter transistor; and 
 wherein the drain of the second differential input transistor is electrically coupled to the source of the second filter transistor. 
 
   
   
     12. The circuit of  claim 1 , wherein a differential output of the differential circuit is electrically coupled to nodes selected from a group consisting of: the source of the first transistor and the source of the second transistor; and the drain of the first transistor and the drain of the second transistor. 
   
   
     13. A differential electrical filter operable to create a pair of complex poles, the differential electrical filter consisting essentially of:
 a first transistor with a gate, a source and a drain; 
 a second transistor with a gate, a source and a drain; 
 a first tuning capacitor, wherein the first tuning capacitor is electrically coupled between the gate of the first transistor and the source of the first transistor; 
 a second tuning capacitor, wherein the second tuning capacitor is electrically coupled between the gate of the second transistor and the source of the second transistor; 
 a first resistor, wherein the first resistor is electrically coupled to the gate of the first transistor, and wherein a first differential input is electrically coupled to the gate of the first transistor via the first resistor; and 
 a second resistor, wherein the second resistor is electrically coupled to the gate of the second transistor, and wherein a second differential input is electrically coupled to the gate of the second transistor via the second resistor. 
 
   
   
     14. The differential electrical filter of  claim 13 , wherein the differential electrical filter circuit includes a first differential output electrically coupled to the source of the first transistor; and wherein the differential electrical filter circuit includes a second differential output electrically coupled to the source of the second transistor. 
   
   
     15. The differential electrical filter of  claim 13 , wherein the differential electrical filter circuit includes a first differential output electrically coupled to the drain of the first transistor; and wherein the differential electrical filter circuit includes a second differential output electrically coupled to the drain of the second transistor. 
   
   
     16. A cascoded filter, wherein the cascoded filter comprises:
 a first filter stage, wherein the second stage filter is operable to create a first pair of complex poles, and wherein the first filter stage includes:
 a first transistor with a gate, a source and a drain; 
 a second transistor with a gate, a source and a drain; 
 a first tuning capacitor, wherein the first tuning capacitor is electrically coupled between the gate of the first transistor and the source of the first transistor; 
 a second tuning capacitor, wherein the second tuning capacitor is electrically coupled between the gate of the second transistor and the source of the second transistor; 
 a first resistor, wherein the first resistor is electrically coupled to the gate of the first transistor; and a second resistor, wherein the second resistor is electrically coupled to the gate of the second transistor; 
 
 a second filter stage, wherein the second stage filter is operable to create a second pair of complex poles, and wherein the second filter stage includes:
 a third transistor with a gate, a source and a drain; 
 a fourth transistor with a gate, a source and a drain; 
 a third tuning capacitor, wherein the third tuning capacitor is electrically coupled between the gate of the third transistor and the source of the third transistor; 
 a fourth tuning capacitor, wherein the fourth tuning capacitor is electrically coupled between the gate of the fourth transistor and the source of the fourth transistor; 
 a third resistor, wherein the first resistor is electrically coupled to the gate of the third transistor; and a fourth resistor, wherein the fourth resistor is electrically coupled to the gate of the fourth transistor; and wherein the first stage is electrically coupled to the second stage. 
 
 
   
   
     17. The cascoded filter of  claim 16 , wherein the cascoded filter further comprises:
 a differential input stage, wherein the differential input stage is electrically coupled to the first filter stage, and wherein the differential input stage includes:
 a fifth transistor with a gate, a source and a drain; 
 a sixth transistor with a gate, a source and a drain; 
 wherein the gate of the fifth transistor is electrically coupled to a first differential input; and wherein the gate of the sixth transistor is electrically coupled to a second differential input. 
 
 
   
   
     18. The cascoded filter of  claim 17 , wherein the cascoded filter further comprises:
 an common gate stage, wherein the common gate stage is electrically coupled to the first filter stage and the second filter stage, and wherein the common gate stage includes:
 a seventh transistor with a gate, a source and a drain; an eighth transistor with a gate, a source and a drain; 
 wherein the gate of the seventh transistor is electrically coupled to a first bias input; and 
 wherein the gate of the eighth transistor is electrically coupled to a second bias input. 
 
 
   
   
     19. The cascoded filter of  claim 18 , wherein the cascoded filter further comprises:
 a current source, wherein the current source is electrically coupled to the differential input stage. 
 
   
   
     20. The cascoded filter of  claim 18 , wherein a differential output is taken from the source of the third transistor and the source of the fourth transistor.