Method of manufacturing bipolar-complementary metal oxide semiconductor

Abstract

A method of manufacturing a bipolar-complementary metal oxide semiconductor (BiCMOS) is provided. A gate in a CMOS area and a conductive layer pattern defining an opening, which opens an active region in a bipolar transistor area, are simultaneously formed by patterning a gate conductive layer. Thereafter, bipolar transistor manufacturing processes are performed while CMOS manufacturing processes are performed. Accordingly, the number of masks is decreased, and degradation of device characteristics is prevented.

1. A method of manufacturing a bipolar-complementary metal oxide semiconductor (BiCMOS), comprising:
 defining a CMOS area and a bipolar transistor area on a substrate; 
 forming a gate oxide layer on the substrate; 
 forming a gate conductive layer on the gate oxide layer; 
 simultaneously forming a gate in the CMOS area and a conductive layer pattern defining an opening which opens an active region in the bipolar transistor area by patterning the gate conductive layer; 
 simultaneously forming gate spacers on side walls of the gate and spacers on inner walls of the opening; 
 forming a base conductive layer on a resultant structure having the spacers; 
 forming an insulating layer on the base conductive layer; 
 forming an emitter window by etching the insulating layer; 
 forming an emitter conductive layer above the emitter window; 
 forming an emitter by patterning the emitter conductive layer and the insulating layer; 
 forming a base by patterning the base conductive layer; and 
 forming source/drain regions at opposite sides of the gate. 
 
   
   
     2. The method of  claim 1 , further comprising implanting low-concentration ions after forming the gate so that the source/drain regions have a lightly doped drain (LDD) structure. 
   
   
     3. The method of  claim 1 , further comprising implanting low-concentration ions after forming the gate spacers so that the source/drain regions have a lightly doped drain (LDD) structure. 
   
   
     4. The method of  claim 1 , wherein forming the base conductive layer comprises:
 exposing a surface of the substrate by removing the gate oxide layer in the opening; 
 forming an undoped Si layer as a seed layer; and 
 sequentially forming a SiGe layer and a doped SiGe layer on the Si layer. 
 
   
   
     5. The method of  claim 1 , wherein the spacers in the bipolar transistor area and the gate spacers are formed of a material selected from the group consisting of an oxide layer, a nitride layer, an oxynitride layer, and a polysilicon layer. 
   
   
     6. The method of  claim 1 , wherein the gate spacers and the spacers are formed of a polysilicon layer, the method further comprising implanting a dopant into the spacers in the bipolar transistor area so that the spacers in the bipolar transistor area become a doped polysilicon layer. 
   
   
     7. The method of  claim 1 , wherein the gate spacers and the spacers are formed of a polysilicon layer, the method further comprising diffusing a dopant in the base conductive layer so that the spacers in the bipolar transistor area become a doped polysilicon layer. 
   
   
     8. The method of  claim 1 , further comprising re-oxidizing the gate before simultaneously forming the gate spacers and the spacers. 
   
   
     9. The method of  claim 1 , wherein forming the emitter comprises:
 patterning the emitter conductive layer so that a portion of the emitter conductive layer in the CMOS area is removed; and 
 partially removing the insulating layer using a wet etching process so that a portion of the insulating layer between the patterned emitter conductive layer and the base conductive layer remains. 
 
   
   
     10. The method of  claim 1 , wherein forming the base comprises patterning the base conductive layer so that a portion of the base conductive layer in the CMOS area is removed. 
   
   
     11. The method of  claim 1 , wherein forming the source/drain regions comprises:
 performing high-concentration ion-implantation using the gate and the gate spacers as a mask; and 
 performing drive-in of a high-concentration ion-implanted dopant using rapid thermal annealing (RTA), 
 wherein drive-in of a dopant in the emitter is performed simultaneously with drive-in of the high-concentration ion-implanted dopant. 
 
   
   
     12. The method of  claim 1 , further comprising forming an extrinsic base region by implanting ions into the bipolar transistor area while forming the source/drain regions. 
   
   
     13. The method of  claim 1 , further comprising patterning the conductive layer pattern below the base after forming the base. 
   
   
     14. The method of  claim 1 , wherein the base is formed by merging the base conductive layer and the conductive layer pattern. 
   
   
     15. A method of manufacturing a bipolar-complementary metal oxide semiconductor (BiCMOS), comprising:
 defining a CMOS area and a bipolar transistor area on a substrate; 
 forming a gate oxide layer on the substrate; 
 forming a polysilicon gate layer on the gate oxide layer; 
 simultaneously forming a gate in the CMOS area and a conductive layer pattern defining an opening which opens an active region in the bipolar transistor area by patterning the polysilicon gate layer; 
 simultaneously forming gate spacers on side walls of the gate and spacers on inner walls of the opening; 
 forming a SiGe base layer on a resultant structure having the spacers; 
 forming an insulating layer on the SiGe base layer; 
 forming an emitter window by etching the insulating layer; 
 forming a polysilicon emitter layer above the emitter window; 
 forming an emitter by patterning the polysilicon emitter layer and the insulating layer; 
 forming a base by patterning the SiGe base layer and the conductive layer pattern; and 
 forming source/drain regions at opposite sides of the gate by implanting ions into the opposite sides of the gate and performing drive-in of an ion-implanted dopant, 
 wherein drive-in of a dopant in the emitter is performed during the drive-in of the ion-implanted dopant. 
 
   
   
     16. The method of  claim 15 , further comprising forming an extrinsic base region by implanting ions into the bipolar transistor area while forming the source/drain regions. 
   
   
     17. The method of  claim 15 , wherein the base is formed by merging the SiGe base layer and the conductive layer pattern.